research.fit.qmsg

用vhdl语言实现2DPSK数字传输

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Oct 27 08:46:16 2007 " "Info: Processing started: Sat Oct 27 08:46:16 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off research -c research " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off research -c research" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "research EPM1270T144C5 " "Info: Selected device EPM1270T144C5 for design \"research\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144C5 " "Info: Device EPM570T144C5 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144I5 " "Info: Device EPM570T144I5 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144I5 " "Info: Device EPM1270T144I5 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144C5ES " "Info: Device EPM1270T144C5ES is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tsu 2.0 ns " "Info: Assuming a global tsu requirement of 2.0 ns" {  } {  } 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tco 1.0 ns " "Info: Assuming a global tco requirement of 1.0 ns" {  } {  } 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tpd 1.0 ns " "Info: Assuming a global tpd requirement of 1.0 ns" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 18 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 18" {  } { { "research.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/research.v" 2 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass Global clock " "Info: Automatically promoted some destinations of signal \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass " "Info: Destination \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass\" may be non-global or may not use global clock" {  } { { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 10 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "test_pass_buffer_8bit:comb_6\|pass_buffer:comb_4\|dout~12 " "Info: Destination \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_4\|dout~12\" may be non-global or may not use global clock" {  } { { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 6 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "test_pass_buffer_8bit:comb_6\|pass_buffer:comb_5\|dout~12 " "Info: Destination \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_5\|dout~12\" may be non-global or may not use global clock" {  } { { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 6 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "test_pass_buffer_8bit:comb_6\|pass_buffer:comb_6\|dout~12 " "Info: Destination \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_6\|dout~12\" may be non-global or may not use global clock" {  } { { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 6 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "test_pass_buffer_8bit:comb_6\|pass_buffer:comb_7\|dout~12 " "Info: Destination \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_7\|dout~12\" may be non-global or may not use global clock" {  } { { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 6 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "test_pass_buffer_8bit:comb_6\|pass_buffer:comb_8\|dout~12 " "Info: Destination \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_8\|dout~12\" may be non-global or may not use global clock" {  } { { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 6 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "test_pass_buffer_8bit:comb_6\|pass_buffer:comb_9\|dout~12 " "Info: Destination \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_9\|dout~12\" may be non-global or may not use global clock" {  } { { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 6 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "test_pass_buffer_8bit:comb_6\|pass_buffer:comb_10\|dout~12 " "Info: Destination \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_10\|dout~12\" may be non-global or may not use global clock" {  } { { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 6 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|dout~12 " "Info: Destination \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|dout~12\" may be non-global or may not use global clock" {  } { { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 6 -1 0 } }  } 0}  } { { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 10 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Info: Moving registers into LUTs to improve timing and density" {  } {  } 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "" "Info: Finished moving registers into LUTs" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.492 ns register pin " "Info: Estimated most critical path is register to pin delay of 3.492 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|out1 1 REG LAB_X10_Y10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X10_Y10; Fanout = 1; REG Node = 'test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|out1'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "" { test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|out1 } "NODE_NAME" } "" } } { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.595 ns) 0.595 ns test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|dout~12 2 COMB LAB_X10_Y10 1 " "Info: 2: + IC(0.000 ns) + CELL(0.595 ns) = 0.595 ns; Loc. = LAB_X10_Y10; Fanout = 1; COMB Node = 'test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|dout~12'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "0.595 ns" { test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|out1 test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|dout~12 } "NODE_NAME" } "" } } { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.575 ns) + CELL(2.322 ns) 3.492 ns led_out\[7\] 3 PIN PIN_122 0 " "Info: 3: + IC(0.575 ns) + CELL(2.322 ns) = 3.492 ns; Loc. = PIN_122; Fanout = 0; PIN Node = 'led_out\[7\]'" {  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "2.897 ns" { test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|dout~12 led_out[7] } "NODE_NAME" } "" } } { "research.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/research.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.917 ns 83.53 % " "Info: Total cell delay = 2.917 ns ( 83.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.575 ns 16.47 % " "Info: Total interconnect delay = 0.575 ns ( 16.47 % )" {  } {  } 0}  } { { "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" "" { Report "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research_cmp.qrpt" Compiler "research" "UNKNOWN" "V1" "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/db/research.quartus_db" { Floorplan "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/" "" "3.492 ns" { test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|out1 test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|dout~12 led_out[7] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "Info: Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and/or routability requirements required full optimization" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 27 08:46:18 2007 " "Info: Processing ended: Sat Oct 27 08:46:18 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}