research.map.qmsg

用vhdl语言实现2DPSK数字传输

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Oct 27 08:46:13 2007 " "Info: Processing started: Sat Oct 27 08:46:13 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off research -c research " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off research -c research" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../Creativity/key_buffer.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../Creativity/key_buffer.v" { { "Info" "ISGN_ENTITY_NAME" "1 key_buffer " "Info: Found entity 1: key_buffer" {  } { { "../Creativity/key_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/key_buffer.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../Creativity/pass_buffer.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../Creativity/pass_buffer.v" { { "Info" "ISGN_ENTITY_NAME" "1 pass_buffer " "Info: Found entity 1: pass_buffer" {  } { { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../Creativity/my_trigger.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../Creativity/my_trigger.v" { { "Info" "ISGN_ENTITY_NAME" "1 my_trigger " "Info: Found entity 1: my_trigger" {  } { { "../Creativity/my_trigger.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/my_trigger.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../Creativity/dig_filter.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../Creativity/dig_filter.v" { { "Info" "ISGN_ENTITY_NAME" "1 dig_filter " "Info: Found entity 1: dig_filter" {  } { { "../Creativity/dig_filter.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/dig_filter.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../Creativity/generate_dm.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../Creativity/generate_dm.v" { { "Info" "ISGN_ENTITY_NAME" "1 generate_dm " "Info: Found entity 1: generate_dm" {  } { { "../Creativity/generate_dm.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/generate_dm.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test_pass_buffer_8bit.v 2 2 " "Info: Found 2 design units, including 2 entities, in source file test_pass_buffer_8bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 test_pass_buffer_8bit " "Info: Found entity 1: test_pass_buffer_8bit" {  } { { "test_pass_buffer_8bit.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/test_pass_buffer_8bit.v" 3 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 pass_buffer_8bit " "Info: Found entity 2: pass_buffer_8bit" {  } { { "test_pass_buffer_8bit.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/test_pass_buffer_8bit.v" 23 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "generate_led.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file generate_led.v" { { "Info" "ISGN_ENTITY_NAME" "1 generate_led " "Info: Found entity 1: generate_led" {  } { { "generate_led.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/generate_led.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "research.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file research.v" { { "Info" "ISGN_ENTITY_NAME" "1 research " "Info: Found entity 1: research" {  } { { "research.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/research.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "research " "Info: Elaborating entity \"research\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VERI_PORT_DELIBERATELY_NOT_CONNECTED" "lock (null) research.v(12) " "Info: (10265) Verilog HDL Module Instantiation information at research.v(12): instance \"(null)\" connects port \"lock\" to an empty expression" {  } { { "research.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/research.v" 12 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "key_buffer key_buffer:comb_4 " "Info: Elaborating entity \"key_buffer\" for hierarchy \"key_buffer:comb_4\"" {  } { { "research.v" "comb_4" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/research.v" 10 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "generate_led generate_led:comb_5 " "Info: Elaborating entity \"generate_led\" for hierarchy \"generate_led:comb_5\"" {  } { { "research.v" "comb_5" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/research.v" 11 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "test_pass_buffer_8bit test_pass_buffer_8bit:comb_6 " "Info: Elaborating entity \"test_pass_buffer_8bit\" for hierarchy \"test_pass_buffer_8bit:comb_6\"" {  } { { "research.v" "comb_6" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/research.v" 12 -1 0 } }  } 0}