research.v

来自「用vhdl语言实现2DPSK数字传输」· Verilog 代码 · 共 15 行

module research (clk,reset,change,led_out);
input clk;
input change;
input reset;
output [7:0] led_out;

wire [7:0] q_int;
wire change_int;

key_buffer (.clk(clk),.key_in(change),.key_out(change_int));
generate_led (.reset(reset),.clk_m(clk),.q(q_int));
test_pass_buffer_8bit (.change(change_int),.din(q_int),.dout(led_out),.lock());

endmodule