research.qsf

用vhdl语言实现2DPSK数字传输

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		research_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:38:45  OCTOBER 24, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 5.0
set_global_assignment -name VERILOG_FILE ../Creativity/key_buffer.v
set_global_assignment -name VERILOG_FILE ../Creativity/pass_buffer.v
set_global_assignment -name VERILOG_FILE ../Creativity/my_trigger.v
set_global_assignment -name VERILOG_FILE ../Creativity/dig_filter.v
set_global_assignment -name VERILOG_FILE ../Creativity/generate_dm.v
set_global_assignment -name VECTOR_WAVEFORM_FILE research.sim.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE generate_dm.sim.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE dig_filter.vwf
set_global_assignment -name VERILOG_FILE test_pass_buffer_8bit.v
set_global_assignment -name VECTOR_WAVEFORM_FILE test_pass_buffer_8bit.vwf
set_global_assignment -name VERILOG_FILE generate_led.v
set_global_assignment -name VERILOG_FILE research.v
set_global_assignment -name VECTOR_WAVEFORM_FILE research.vwf

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_42 -to change
set_location_assignment PIN_18 -to clk
set_location_assignment PIN_43 -to reset
set_location_assignment PIN_131 -to led_out[0]
set_location_assignment PIN_130 -to led_out[1]
set_location_assignment PIN_129 -to led_out[2]
set_location_assignment PIN_127 -to led_out[3]
set_location_assignment PIN_125 -to led_out[4]
set_location_assignment PIN_124 -to led_out[5]
set_location_assignment PIN_123 -to led_out[6]
set_location_assignment PIN_122 -to led_out[7]

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name TOP_LEVEL_ENTITY research

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EPM1270T144C5
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

# Simulator Assignments
# =====================
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name VECTOR_INPUT_SOURCE research.vwf