research.flow.rpt

用vhdl语言实现2DPSK数字传输

Flow report for research
Sat Oct 27 08:46:22 2007
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Elapsed Time
  5. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+--------------------------------------------------------------------+
; Flow Summary                                                       ;
+-------------------------+------------------------------------------+
; Flow Status             ; Successful - Sat Oct 27 08:46:22 2007    ;
; Quartus II Version      ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name           ; research                                 ;
; Top-level Entity Name   ; research                                 ;
; Family                  ; MAX II                                   ;
; Device                  ; EPM1270T144C5                            ;
; Timing Models           ; Final                                    ;
; Met timing requirements ; No                                       ;
; Total logic elements    ; 22 / 1,270 ( 1 % )                       ;
; Total pins              ; 11 / 116 ( 9 % )                         ;
; Total virtual pins      ; 0                                        ;
; UFM blocks              ; 0 / 1 ( 0 % )                            ;
+-------------------------+------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 10/27/2007 08:46:13 ;
; Main task         ; Compilation         ;
; Revision Name     ; research            ;
+-------------------+---------------------+


+-------------------------------------+
; Flow Elapsed Time                   ;
+----------------------+--------------+
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:02     ;
; Fitter               ; 00:00:02     ;
; Assembler            ; 00:00:01     ;
; Timing Analyzer      ; 00:00:01     ;
; Total                ; 00:00:06     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off research -c research
quartus_fit --read_settings_files=off --write_settings_files=off research -c research
quartus_asm --read_settings_files=off --write_settings_files=off research -c research
quartus_tan --read_settings_files=off --write_settings_files=off research -c research