research.tan.summary

用vhdl语言实现2DPSK数字传输

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 2.078 ns
From           : reset
To             : generate_led:comb_5|q[1]
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 15.041 ns
From           : test_pass_buffer_8bit:comb_6|pass_buffer:comb_4|out1
To             : led_out[0]
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -1.209 ns
From           : change
To             : key_buffer:comb_4|state.s3
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 304.04 MHz ( period = 3.289 ns )
From           : key_buffer:comb_4|state.s3
To             : key_buffer:comb_4|state.start
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : generate_led:comb_5|q[6]
To             : test_pass_buffer_8bit:comb_6|pass_buffer:comb_10|out1
From Clock     : clk
To Clock       : clk
Failed Paths   : 8

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 8

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