prev_cmp_dpsk.fit.qmsg

用vhdl语言实现2DPSK数字传输

{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk_50MHz Global clock in PIN 18 " "Info: Automatically promoted signal \"clk_50MHz\" to use Global clock in PIN 18" {  } { { "DPSK.bdf" "" { Schematic "C:/Documents and Settings/s/桌面/Newest/设计/DPSK/DPSK.bdf" { { 216 -104 64 232 "clk_50MHz" "" } { -24 56 120 -8 "clk_50MHz" "" } { 208 64 125 224 "clk_50MHz" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "lcdcont:inst1\|clockdiv:div\|clock_int Global clock " "Info: Automatically promoted some destinations of signal \"lcdcont:inst1\|clockdiv:div\|clock_int\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "E " "Info: Destination \"E\" may be non-global or may not use global clock" {  } { { "DPSK.bdf" "" { Schematic "C:/Documents and Settings/s/桌面/Newest/设计/DPSK/DPSK.bdf" { { 32 440 616 48 "E" "" } } } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcdcont:inst1\|clockdiv:div\|clock_int " "Info: Destination \"lcdcont:inst1\|clockdiv:div\|clock_int\" may be non-global or may not use global clock" {  } { { "../LCD/lcd_zifu/clockdiv.vhd" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/LCD/lcd_zifu/clockdiv.vhd" 27 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "../LCD/lcd_zifu/clockdiv.vhd" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/LCD/lcd_zifu/clockdiv.vhd" 27 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "DPSK_shell:inst\|LCM_pre:comb_9\|clk_ser Global clock " "Info: Automatically promoted signal \"DPSK_shell:inst\|LCM_pre:comb_9\|clk_ser\" to use Global clock" {  } { { "../Creativity/LCM_pre.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/LCM_pre.v" 6 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "DPSK_shell:inst\|clk_div:comb_5\|Equal0 Global clock " "Info: Automatically promoted some destinations of signal \"DPSK_shell:inst\|clk_div:comb_5\|Equal0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "DPSK_shell:inst\|clk_div:comb_5\|qa\[0\] " "Info: Destination \"DPSK_shell:inst\|clk_div:comb_5\|qa\[0\]\" may be non-global or may not use global clock" {  } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "DPSK_shell:inst\|clk_div:comb_5\|qa\[1\] " "Info: Destination \"DPSK_shell:inst\|clk_div:comb_5\|qa\[1\]\" may be non-global or may not use global clock" {  } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "DPSK_shell:inst\|clk_div:comb_5\|qa\[2\] " "Info: Destination \"DPSK_shell:inst\|clk_div:comb_5\|qa\[2\]\" may be non-global or may not use global clock" {  } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "DPSK_shell:inst\|clk_div:comb_5\|qa\[3\] " "Info: Destination \"DPSK_shell:inst\|clk_div:comb_5\|qa\[3\]\" may be non-global or may not use global clock" {  } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "DPSK_shell:inst\|clk_div:comb_5\|qa\[4\] " "Info: Destination \"DPSK_shell:inst\|clk_div:comb_5\|qa\[4\]\" may be non-global or may not use global clock" {  } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "DPSK_shell:inst\|clk_div:comb_5\|qa\[5\] " "Info: Destination \"DPSK_shell:inst\|clk_div:comb_5\|qa\[5\]\" may be non-global or may not use global clock" {  } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "DPSK_shell:inst\|clk_div:comb_5\|qa\[6\] " "Info: Destination \"DPSK_shell:inst\|clk_div:comb_5\|qa\[6\]\" may be non-global or may not use global clock" {  } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "DPSK_shell:inst\|clk_div:comb_5\|qa\[7\] " "Info: Destination \"DPSK_shell:inst\|clk_div:comb_5\|qa\[7\]\" may be non-global or may not use global clock" {  } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "DPSK_shell:inst\|clk_div:comb_5\|qa\[8\] " "Info: Destination \"DPSK_shell:inst\|clk_div:comb_5\|qa\[8\]\" may be non-global or may not use global clock" {  } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 13 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Extra Info: Moving registers into LUTs to improve timing and density" {  } {  } 1 0 "Moving registers into LUTs to improve timing and density" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0 0 "Started processing fast register assignments" 0 0 "" 0}