test_demodulate.v

来自「用vhdl语言实现2DPSK数字传输」· Verilog 代码 · 共 22 行

module test_demodulate(reset,clk,dout,syn_clk,din);
input clk,reset;
output dout;
output syn_clk;
output din;

wire din;
wire syn_clk;
reg [3:0] q;
wire clk_dm;

synchronize (.m(din),.clk_in(clk),.clk_out(syn_clk));
generate_dm (.reset(reset),.clk_m(clk_dm),.dm(din));
shift_detect (.clk(clk_dm),.m1(din),.a(dout));

assign clk_dm=(q==4'b1111);
always@(posedge clk)
begin
q=q+1;
end

endmodule