📄 dpsk.map.rpt
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Analysis & Synthesis report for DPSK
Wed Oct 31 11:32:32 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. State Machine - |DPSK|DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_43|state
8. State Machine - |DPSK|DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_42|state
9. State Machine - |DPSK|DPSK_shell:inst|key_buffer:comb_11|state
10. State Machine - |DPSK|DPSK_shell:inst|key_buffer:comb_6|state
11. State Machine - |DPSK|lcdcont:inst1|lcd:mylcd|state
12. Registers Removed During Synthesis
13. General Register Statistics
14. Multiplexer Restructuring Statistics (Restructuring Performed)
15. Parameter Settings for User Entity Instance: lcdcont:inst1
16. Parameter Settings for User Entity Instance: lcdcont:inst1|lcd:mylcd
17. Parameter Settings for User Entity Instance: DPSK_shell:inst|key_buffer:comb_6
18. Parameter Settings for User Entity Instance: DPSK_shell:inst|key_buffer:comb_11
19. Parameter Settings for User Entity Instance: DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_42
20. Parameter Settings for User Entity Instance: DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_43
21. Analysis & Synthesis Messages
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; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Oct 31 11:32:32 2007 ;
; Quartus II Version ; 7.1 Build 156 04/30/2007 SJ Full Version ;
; Revision Name ; DPSK ;
; Top-level Entity Name ; DPSK ;
; Family ; MAX II ;
; Total logic elements ; 310 ;
; Total pins ; 51 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 ;
+-----------------------------+------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EPM1270T144C5 ; ;
; Top-level entity name ; DPSK ; DPSK ;
; Family name ; MAX II ; Stratix ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- MAX II ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Use smart compilation ; Off ; Off ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------+
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