dpsk.fit.summary

来自「用vhdl语言实现2DPSK数字传输」· SUMMARY 代码 · 共 12 行

Fitter Status : Successful - Wed Oct 31 11:32:45 2007
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : DPSK
Top-level Entity Name : DPSK
Family : MAX II
Device : EPM1270T144C5
Timing Models : Final
Total logic elements : 271 / 1,270 ( 21 % )
Total pins : 51 / 116 ( 44 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )