dpsk.qsf

用vhdl语言实现2DPSK数字传输

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		DPSK_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:11:31  OCTOBER 14, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 7.1
set_global_assignment -name VHDL_FILE ../Creativity/lcdcont.vhd
set_global_assignment -name VHDL_FILE ../Creativity/lcd.vhd
set_global_assignment -name VHDL_FILE ../LCD/lcd_zifu/shifter.vhd
set_global_assignment -name VHDL_FILE ../LCD/lcd_zifu/cir_shifter.vhd
set_global_assignment -name VHDL_FILE ../LCD/lcd_zifu/clockdiv.vhd
set_global_assignment -name VERILOG_FILE ../Creativity/LCM_pre.v
set_global_assignment -name VERILOG_FILE ../Creativity/generate_dm.v
set_global_assignment -name VERILOG_FILE ../Creativity/pass_buffer_8bit.v
set_global_assignment -name VECTOR_WAVEFORM_FILE instantiation_1to4.vwf
set_global_assignment -name VERILOG_FILE ../Creativity/instantiation_1to4.v
set_global_assignment -name BDF_FILE test.bdf
set_global_assignment -name VERILOG_FILE ../Creativity/synchronize.v
set_global_assignment -name VERILOG_FILE ../Creativity/channel_choice.v
set_global_assignment -name VERILOG_FILE ../Creativity/clk_div.v
set_global_assignment -name VERILOG_FILE ../Creativity/demodulate.v
set_global_assignment -name VERILOG_FILE ../Creativity/diff_code.v
set_global_assignment -name VERILOG_FILE ../Creativity/dig_display.v
set_global_assignment -name VERILOG_FILE ../Creativity/dig_filter.v
set_global_assignment -name VERILOG_FILE ../Creativity/get_edge.v
set_global_assignment -name VERILOG_FILE ../Creativity/key_buffer.v
set_global_assignment -name VERILOG_FILE ../Creativity/LCM.v
set_global_assignment -name VERILOG_FILE ../Creativity/modulate.v
set_global_assignment -name VERILOG_FILE ../Creativity/my_dff.v
set_global_assignment -name VERILOG_FILE ../Creativity/my_shift_reg.v
set_global_assignment -name VERILOG_FILE ../Creativity/my_syn_counter.v
set_global_assignment -name VERILOG_FILE ../Creativity/my_trigger.v
set_global_assignment -name VERILOG_FILE ../Creativity/pass_buffer.v
set_global_assignment -name VERILOG_FILE ../Creativity/phase_counter.v
set_global_assignment -name VERILOG_FILE ../Creativity/phase_table.v
set_global_assignment -name VERILOG_FILE ../Creativity/shift_detect.v
set_global_assignment -name VECTOR_WAVEFORM_FILE diff_code.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE report/diff_code_function.sim.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE report/diff_code_timing.sim.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE my_dff.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE report/my_dff_function.sim.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE report/my_dff_timing.sim.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE report/my_dff_timing1.sim.vwf
set_global_assignment -name MIF_FILE phase_table.mif
set_global_assignment -name VECTOR_WAVEFORM_FILE pass_buffer.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE report/pass_buffer_function.sim.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE channel_choice.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE report/channel_choice_function.sim.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE modulate.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE demodulate.vwf
set_global_assignment -name VERILOG_FILE test_demodulate.v
set_global_assignment -name VECTOR_WAVEFORM_FILE test_demodulate.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE get_edge.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE synchronize.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE my_syn_counter.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE test_synchronize.sim.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE test_synchronize1.sim.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE clk_div.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE clk_div.sim.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE DPSK.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE DPSK.sim.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE LCM.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE LCM.sim.vwf
set_global_assignment -name VERILOG_FILE ../Creativity/DPSK_shell.v
set_global_assignment -name BDF_FILE DPSK.bdf
set_global_assignment -name VERILOG_FILE generate_a.v
set_global_assignment -name VERILOG_FILE generate_m.v
set_global_assignment -name VECTOR_WAVEFORM_FILE shift_detect.vwf

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_118 -to E
set_location_assignment PIN_120 -to RS
set_location_assignment PIN_119 -to RW
set_location_assignment PIN_121 -to cont
set_location_assignment PIN_43 -to change
set_location_assignment PIN_18 -to clk_50MHz
set_location_assignment PIN_24 -to dig_code_d[0]
set_location_assignment PIN_22 -to dig_code_d[1]
set_location_assignment PIN_28 -to dig_code_d[2]
set_location_assignment PIN_27 -to dig_code_d[3]
set_location_assignment PIN_29 -to dig_code_d[4]
set_location_assignment PIN_21 -to dig_code_d[5]
set_location_assignment PIN_23 -to dig_code_d[6]
set_location_assignment PIN_14 -to dig_code_m[0]
set_location_assignment PIN_16 -to dig_code_m[1]
set_location_assignment PIN_12 -to dig_code_m[2]
set_location_assignment PIN_13 -to dig_code_m[3]
set_location_assignment PIN_11 -to dig_code_m[4]
set_location_assignment PIN_20 -to dig_code_m[5]
set_location_assignment PIN_15 -to dig_code_m[6]
set_location_assignment PIN_75 -to din_a2
set_location_assignment PIN_77 -to dout
set_location_assignment PIN_117 -to lcm_out[0]
set_location_assignment PIN_114 -to lcm_out[1]
set_location_assignment PIN_113 -to lcm_out[2]
set_location_assignment PIN_112 -to lcm_out[3]
set_location_assignment PIN_111 -to lcm_out[4]
set_location_assignment PIN_110 -to lcm_out[5]
set_location_assignment PIN_109 -to lcm_out[6]
set_location_assignment PIN_108 -to lcm_out[7]
set_location_assignment PIN_87 -to phase_out[0]
set_location_assignment PIN_86 -to phase_out[1]
set_location_assignment PIN_85 -to phase_out[2]
set_location_assignment PIN_84 -to phase_out[3]
set_location_assignment PIN_81 -to phase_out[4]
set_location_assignment PIN_80 -to phase_out[5]
set_location_assignment PIN_79 -to phase_out[6]
set_location_assignment PIN_78 -to phase_out[7]
set_location_assignment PIN_42 -to reset
set_location_assignment PIN_131 -to led_light[0]
set_location_assignment PIN_130 -to led_light[1]
set_location_assignment PIN_129 -to led_light[2]
set_location_assignment PIN_127 -to led_light[3]
set_location_assignment PIN_125 -to led_light[4]
set_location_assignment PIN_124 -to led_light[5]
set_location_assignment PIN_123 -to led_light[6]
set_location_assignment PIN_122 -to led_light[7]
set_location_assignment PIN_76 -to din_m2
set_location_assignment PIN_30 -to channel_choide_a
set_location_assignment PIN_31 -to channel_choice_m
set_location_assignment PIN_88 -to dout_a1

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name TOP_LEVEL_ENTITY DPSK
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
set_global_assignment -name FAMILY "MAX II"

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EPM1270T144C5
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

# Assembler Assignments
# =====================
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF

# Simulator Assignments
# =====================
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS ON
set_global_assignment -name VECTOR_INPUT_SOURCE shift_detect.vwf