phase_counter.v

来自「用vhdl语言实现2DPSK数字传输」· Verilog 代码 · 共 17 行

module phase_counter(clk,clr,syn,s);
input clk,clr,syn;
output [4:0] s;

wire [4:0] c;
wire [4:0] s;
wire load;
wire [4:0] d;

assign load=1'b1;
assign d=5'b00000;

my_syn_counter (.clk(clk),.clr(clr),.load(load),.d(d),.q(c),.cin());
xor (s[4],c[4],syn);
assign  s[3:0]=c[3:0];

endmodule