instantiation_1to4.v

来自「用vhdl语言实现2DPSK数字传输」· Verilog 代码 · 共 10 行

module instantiation_1to4(a,b,c);
input [3:0] a;
input [3:0] b;
output [3:0] c;

and (c,a,b);

endmodule

//failed to convert from 1 bit to four bit;