diff_code.v

来自「用vhdl语言实现2DPSK数字传输」· Verilog 代码 · 共 14 行

module diff_code(a,clk,b);
input a,clk;
output b;
wire b;
wire bt;

xor (bt, a, b);
my_dff (.clk(clk),.d(bt),.q(b),.qb()); 
//always @(posedge clkt)
//begin
//b=bt;
//end

endmodule