synchronize.v

来自「用vhdl语言实现2DPSK数字传输」· Verilog 代码 · 共 29 行

module synchronize(m,clk_in,clk_out);
//clk_in 采用clk_dig的64倍，即clk_phase,(这也相当于m波特率的32倍,即N=16);
input m,clk_in;
output clk_out;

wire clk_int;
wire din;
wire load,_edge;
reg [3:0] q;
assign load=~_edge;

dig_filter (.clk(clk_in),.din(m),.out(din));
get_edge (.clk(clk_in),.din(din),._edge(_edge),.dout());

always @(posedge clk_in)
begin
if(load==0) q=4'b1000;
else q=q+1;
end

assign clk_out=(q==4'b1111); 

endmodule