phase_table.v

来自「用vhdl语言实现2DPSK数字传输」· Verilog 代码 · 共 47 行

module phase_table(clk,address,qout);
input clk;
input [4:0] address;
output [7:0] qout;

reg [7:0] qout;

always @(posedge clk)
begin
case (address)
'b00000:qout=127;
'b00001:qout=152;
'b00010:qout=176;
'b00011:qout=198;
'b00100:qout=218;
'b00101:qout=233;
'b00110:qout=245;
'b00111:qout=252;
'b01000:qout=255;
'b01001:qout=253;
'b01010:qout=245;
'b01011:qout=233;
'b01100:qout=218;
'b01101:qout=198;
'b01110:qout=176;
'b01111:qout=152;
'b10000:qout=127;
'b10001:qout=103;
'b10010:qout=79;
'b10011:qout=57;
'b10100:qout=37;
'b10101:qout=21;
'b10110:qout=10;
'b10111:qout=2;
'b11000:qout=0;
'b11001:qout=2;
'b11010:qout=10;
'b11011:qout=21;
'b11100:qout=37;
'b11101:qout=57;
'b11110:qout=79;
'b11111:qout=103;
endcase
end

endmodule