my_shift_reg.v

用vhdl语言实现2DPSK数字传输

module my_shift_reg(clk,d,q);
input clk,d;
output [4:0] q;

reg [4:0] q;

//my_dff(.clk(clk),.d(d),.q(q[4]),.qb());
//my_dff(.clk(clk),.d(q[4]),.q(q[3]),.qb());
//my_dff(.clk(clk),.d(q[3]),.q(q[2]),.qb());
//my_dff(.clk(clk),.d(q[2]),.q(q[1]),.qb());
//my_dff(.clk(clk),.d(q[1]),.q(q[0]),.qb());

//循环移位；
//wire temp;
//always @(posedge clk)
//begin
//temp=q[0];
//q=q>>1;
//q[4]=temp;
//end

//单向移位；
always @(posedge clk)
begin
q=q>>1;
q[4]=d;
end

endmodule