key_buffer.v

用vhdl语言实现2DPSK数字传输

module key_buffer(clk,key_in,key_out);
//经消抖电路处理后，输出一个时钟长的标准脉冲，低电平有效；
input clk,key_in;
output key_out;
reg [1:0] state;
//parameter start='d0,s1='d1,s2='d2,s3='d3;
parameter start=2'b00,s1=2'b01,s2=2'b10,s3=2'b11;
assign key_out=~(state==s2);

always@(posedge clk)
begin
if(key_in==1) state<=start;
else
case(state)
start: state<=s1;
s1: state<=s2;
s2: state<=s3;
s3: state<=s3;
default: state<=start;
endcase
end
endmodule