get_edge.v

用vhdl语言实现2DPSK数字传输

module get_edge(clk,din,_edge,dout);
input clk,din;
output dout,_edge;

wire dout,_edge;
wire delay;

my_dff (.clk(clk),.d(din),.q(dout),.qb());
my_dff (.clk(clk),.d(dout),.q(delay),.qb());
xor (_edge,dout,delay);

endmodule