demodulate.v

来自「用vhdl语言实现2DPSK数字传输」· Verilog 代码 · 共 19 行

module demodulate(clk,din,dout);
input clk,din;
output dout;

//wire syn_clk;
wire clk_int;
reg [3:0] q;
//synchronize (.m(din),.clk_in(clk),.clk_out(syn_clk));
//shift_detect (.clk(syn_clk),.m1(din),.a(dout));
shift_detect (.clk(clk_int),.m1(din),.a(dout));

always @(posedge clk)
begin
q=q+1;
end

assign clk_int=(q==4'b1111);

endmodule