my_syn_counter.v

用vhdl语言实现2DPSK数字传输

module my_syn_counter(clk,clr,load,d,q,cin);
input clk,clr,load;
input [4:0] d;
output [4:0] q;
output cin;

reg [4:0] q;

assign cin=(q==5'b11111);

always @(posedge clk)
begin
if(clr==0)	q=5'b00000;
else if(load==0)	q=d;
else q=q+1;
end

endmodule