my_dff.v

来自「用vhdl语言实现2DPSK数字传输」· Verilog 代码 · 共 13 行

module my_dff(clk,d,q,qb);
input clk,d;
output q,qb;

reg q,qb;

always @(posedge clk)
begin 
q=d;
qb=~q;
end

endmodule