dig_display.v

来自「用vhdl语言实现2DPSK数字传输」· Verilog 代码 · 共 25 行

//这是数码管的译码模块；
module dig_display(a,dig_code);
input a;
output [6:0] dig_code;
reg [6:0] dig_code;

always @(a)
begin
case (a)
0:dig_code=7'b1111110;
1:dig_code=7'b0110000;
endcase
end

endmodule


//bit	high	low	
//a:	pin15,	pin23;
//b:	pin20,	pin21;
//c:	pin11,	pin29;
//d:	pin13,	pin27;
//e:	pin12,	pin28;
//f:	pin16,	pin22;
//g:	pin14,	pin24;