dpsk.v

用vhdl语言实现2DPSK数字传输

module DPSK(clk_50MHz,din_a1,din_a2,din_m1,phase_out,dout,
		change,channel_choice,
		dig_code_m,dig_code_d,
		led_light,
//		reset,RW,RS,E,cont,lcm_out);
		clk_lcm_pre,wave_out);
input clk_50MHz,din_a1,din_a2,din_m1;
input channel_choice,change;
//input reset;
output dout;//由母版完成解调后输出的数字信号;
output [7:0] phase_out;
output [6:0] dig_code_m;
output [6:0] dig_code_d;
output [7:0] led_light;
//output [7:0] lcm_out;
//output RW,RS,E,cont;
output clk_lcm_pre;
output [7:0] wave_out;

wire dout;
wire [7:0] phase_out;
wire lock;
wire change_int;
wire reset_int;
wire clk_phase,clk_lcd,clk_diff;
wire din_a,din_m;
wire din_a_buf,dout_buf;
wire din_m2;
wire [4:0] wave_in;

assign din_m2=1'b0;

clk_div (.clk_50MHz(clk_50MHz),.clk_phase(clk_phase),.clk_lcd(clk_lcd),.clk_diff(clk_diff));
//channel choice;
channel_choice  u1(.channel(channel_choice),.d_int(din_a2),.d_ext(din_a1),.q(din_a));
channel_choice  u2(.channel(channel_choice),.d_int(din_m2),.d_ext(din_m1),.q(din_m));
//entity of modulate and demodulate;
modulate (.a(din_a),.clk_phase(clk_phase),.clk_dig(clk_diff),.phase_out(phase_out),.phase_state(wave_in));
demodulate (.clk(clk_phase),.din(din_m),.dout(dout));

//buffer and display;
//key_buffer (.clk(clk_diff),.key_in(reset),.key_out(reset_int));
key_buffer (.clk(clk_diff),.key_in(change),.key_out(change_int));
pass_buffer u5(.change(change_int),.din(din_a),.dout(din_a_buf),.lock(lock));
pass_buffer u6(.change(change_int),.din(dout),.dout(dout_buf),.lock());

///////////////////////////////////
pass_buffer_8bit u7(.change(change_int),.din(phase_out),.dout(led_light),.lock());
/////////////////////////////////////
dig_display  u3(.a(din_a_buf),.dig_code(dig_code_m));
dig_display  u4(.a(dout_buf),.dig_code(dig_code_d));
//LCM (.reset(reset_int),.clk_lcd(clk_lcd),.lock(lock),.wave_in(wave_in),.RW(RW),.RS(RS),.E(E),.cont(cont),.data_out(lcm_out));
LCM_pre (.clk_lcd_base(clk_lcd),.lock(lock),.wave_in(wave_in),.clk_lcm(clk_lcm_pre),.wave_out(wave_out));
endmodule