📄 elc_clock.fit.qmsg
字号:
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "18.567 ns register register " "Info: Estimated most critical path is register to register delay of 18.567 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns hour\[4\] 1 REG LAB_X23_Y11 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X23_Y11; Fanout = 14; REG Node = 'hour\[4\]'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { hour[4] } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 86 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.153 ns) + CELL(0.575 ns) 1.728 ns lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[1\]~COUTCOUT1 2 COMB LAB_X22_Y10 1 " "Info: 2: + IC(1.153 ns) + CELL(0.575 ns) = 1.728 ns; Loc. = LAB_X22_Y10; Fanout = 1; COMB Node = 'lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[1\]~COUTCOUT1'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.728 ns" { hour[4] lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[1]~COUTCOUT1 } "NODE_NAME" } } { "db/add_sub_6dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_6dc.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 2.336 ns lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[2\]~39 3 COMB LAB_X22_Y10 2 " "Info: 3: + IC(0.000 ns) + CELL(0.608 ns) = 2.336 ns; Loc. = LAB_X22_Y10; Fanout = 2; COMB Node = 'lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[2\]~39'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.608 ns" { lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[1]~COUTCOUT1 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~39 } "NODE_NAME" } } { "db/add_sub_6dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_6dc.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.385 ns) + CELL(0.575 ns) 3.296 ns lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[2\]~36COUT1 4 COMB LAB_X22_Y10 2 " "Info: 4: + IC(0.385 ns) + CELL(0.575 ns) = 3.296 ns; Loc. = LAB_X22_Y10; Fanout = 2; COMB Node = 'lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[2\]~36COUT1'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.960 ns" { lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~39 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~36COUT1 } "NODE_NAME" } } { "db/add_sub_6dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_6dc.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 3.376 ns lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[2\]~32COUT1 5 COMB LAB_X22_Y10 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 3.376 ns; Loc. = LAB_X22_Y10; Fanout = 2; COMB Node = 'lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[2\]~32COUT1'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~36COUT1 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~32COUT1 } "NODE_NAME" } } { "db/add_sub_6dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_6dc.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 3.456 ns lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[2\]~34COUT1 6 COMB LAB_X22_Y10 1 " "Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 3.456 ns; Loc. = LAB_X22_Y10; Fanout = 1; COMB Node = 'lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[2\]~34COUT1'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~32COUT1 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~34COUT1 } "NODE_NAME" } } { "db/add_sub_6dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_6dc.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 4.064 ns lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[2\]~29 7 COMB LAB_X22_Y10 8 " "Info: 7: + IC(0.000 ns) + CELL(0.608 ns) = 4.064 ns; Loc. = LAB_X22_Y10; Fanout = 8; COMB Node = 'lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[2\]~29'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.608 ns" { lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~34COUT1 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~29 } "NODE_NAME" } } { "db/add_sub_6dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_6dc.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.303 ns) + CELL(0.590 ns) 4.957 ns lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|StageOut\[16\]~38 8 COMB LAB_X23_Y10 3 " "Info: 8: + IC(0.303 ns) + CELL(0.590 ns) = 4.957 ns; Loc. = LAB_X23_Y10; Fanout = 3; COMB Node = 'lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|StageOut\[16\]~38'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.893 ns" { lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~29 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[16]~38 } "NODE_NAME" } } { "db/alt_u_div_4oe.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/alt_u_div_4oe.tdf" 60 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.533 ns) + CELL(0.432 ns) 5.922 ns lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_4\|add_sub_cella\[2\]~48COUT1 9 COMB LAB_X23_Y10 2 " "Info: 9: + IC(0.533 ns) + CELL(0.432 ns) = 5.922 ns; Loc. = LAB_X23_Y10; Fanout = 2; COMB Node = 'lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_4\|add_sub_cella\[2\]~48COUT1'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.965 ns" { lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[16]~38 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~48COUT1 } "NODE_NAME" } } { "db/add_sub_7dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_7dc.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 6.002 ns lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_4\|add_sub_cella\[2\]~50COUT1 10 COMB LAB_X23_Y10 1 " "Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 6.002 ns; Loc. = LAB_X23_Y10; Fanout = 1; COMB Node = 'lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_4\|add_sub_cella\[2\]~50COUT1'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~48COUT1 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~50COUT1 } "NODE_NAME" } } { "db/add_sub_7dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_7dc.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 6.082 ns lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_4\|add_sub_cella\[2\]~46COUT1 11 COMB LAB_X23_Y10 1 " "Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 6.082 ns; Loc. = LAB_X23_Y10; Fanout = 1; COMB Node = 'lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_4\|add_sub_cella\[2\]~46COUT1'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~50COUT1 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~46COUT1 } "NODE_NAME" } } { "db/add_sub_7dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_7dc.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 6.690 ns lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_4\|add_sub_cella\[2\]~43 12 COMB LAB_X23_Y10 8 " "Info: 12: + IC(0.000 ns) + CELL(0.608 ns) = 6.690 ns; Loc. = LAB_X23_Y10; Fanout = 8; COMB Node = 'lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_4\|add_sub_cella\[2\]~43'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.608 ns" { lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~46COUT1 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~43 } "NODE_NAME" } } { "db/add_sub_7dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_7dc.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.779 ns) + CELL(0.114 ns) 7.583 ns lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|StageOut\[23\]~572 13 COMB LAB_X22_Y10 2 " "Info: 13: + IC(0.779 ns) + CELL(0.114 ns) = 7.583 ns; Loc. = LAB_X22_Y10; Fanout = 2; COMB Node = 'lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|StageOut\[23\]~572'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.893 ns" { lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~43 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[23]~572 } "NODE_NAME" } } { "db/alt_u_div_4oe.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/alt_u_div_4oe.tdf" 60 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.077 ns) + CELL(0.575 ns) 9.235 ns lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_5\|add_sub_cella\[2\]~48COUT1 14 COMB LAB_X22_Y9 1 " "Info: 14: + IC(1.077 ns) + CELL(0.575 ns) = 9.235 ns; Loc. = LAB_X22_Y9; Fanout = 1; COMB Node = 'lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_5\|add_sub_cella\[2\]~48COUT1'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.652 ns" { lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[23]~572 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_5|add_sub_cella[2]~48COUT1 } "NODE_NAME" } } { "db/add_sub_7dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_7dc.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 9.843 ns lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_5\|add_sub_cella\[2\]~43 15 COMB LAB_X22_Y9 6 " "Info: 15: + IC(0.000 ns) + CELL(0.608 ns) = 9.843 ns; Loc. = LAB_X22_Y9; Fanout = 6; COMB Node = 'lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_5\|add_sub_cella\[2\]~43'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.608 ns" { lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_5|add_sub_cella[2]~48COUT1 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_5|add_sub_cella[2]~43 } "NODE_NAME" } } { "db/add_sub_7dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_7dc.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.250 ns) + CELL(0.114 ns) 11.207 ns lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|StageOut\[27\]~568 16 COMB LAB_X23_Y11 4 " "Info: 16: + IC(1.250 ns) + CELL(0.114 ns) = 11.207 ns; Loc. = LAB_X23_Y11; Fanout = 4; COMB Node = 'lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|StageOut\[27\]~568'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.364 ns" { lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_5|add_sub_cella[2]~43 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[27]~568 } "NODE_NAME" } } { "db/alt_u_div_4oe.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/alt_u_div_4oe.tdf" 60 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.007 ns) + CELL(0.575 ns) 12.789 ns lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_6\|add_sub_cella\[2\]~48COUT1 17 COMB LAB_X20_Y11 1 " "Info: 17: + IC(1.007 ns) + CELL(0.575 ns) = 12.789 ns; Loc. = LAB_X20_Y11; Fanout = 1; COMB Node = 'lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_6\|add_sub_cella\[2\]~48COUT1'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.582 ns" { lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[27]~568 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~48COUT1 } "NODE_NAME" } } { "db/add_sub_7dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_7dc.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 12.869 ns lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_6\|add_sub_cella\[2\]~50COUT1 18 COMB LAB_X20_Y11 1 " "Info: 18: + IC(0.000 ns) + CELL(0.080 ns) = 12.869 ns; Loc. = LAB_X20_Y11; Fanout = 1; COMB Node = 'lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_6\|add_sub_cella\[2\]~50COUT1'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~48COUT1 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~50COUT1 } "NODE_NAME" } } { "db/add_sub_7dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_7dc.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 13.477 ns lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_6\|add_sub_cella\[2\]~43 19 COMB LAB_X20_Y11 4 " "Info: 19: + IC(0.000 ns) + CELL(0.608 ns) = 13.477 ns; Loc. = LAB_X20_Y11; Fanout = 4; COMB Node = 'lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_6\|add_sub_cella\[2\]~43'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.608 ns" { lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~50COUT1 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~43 } "NODE_NAME" } } { "db/add_sub_7dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_7dc.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.779 ns) + CELL(0.114 ns) 14.370 ns lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|StageOut\[32\]~567 20 COMB LAB_X19_Y11 8 " "Info: 20: + IC(0.779 ns) + CELL(0.114 ns) = 14.370 ns; Loc. = LAB_X19_Y11; Fanout = 8; COMB Node = 'lpm_divide:Mod2\|lpm_divide_htl:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|StageOut\[32\]~567'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.893 ns" { lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~43 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[32]~567 } "NODE_NAME" } } { "db/alt_u_div_4oe.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/alt_u_div_4oe.tdf" 60 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.085 ns) + CELL(0.292 ns) 15.747 ns Mux36~19 21 COMB LAB_X20_Y8 1 " "Info: 21: + IC(1.085 ns) + CELL(0.292 ns) = 15.747 ns; Loc. = LAB_X20_Y8; Fanout = 1; COMB Node = 'Mux36~19'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.377 ns" { lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[32]~567 Mux36~19 } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 114 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.212 ns) + CELL(0.442 ns) 16.401 ns Mux52~208 22 COMB LAB_X20_Y8 1 " "Info: 22: + IC(0.212 ns) + CELL(0.442 ns) = 16.401 ns; Loc. = LAB_X20_Y8; Fanout = 1; COMB Node = 'Mux52~208'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.654 ns" { Mux36~19 Mux52~208 } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 138 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.362 ns) + CELL(0.292 ns) 17.055 ns Mux52~209 23 COMB LAB_X20_Y8 1 " "Info: 23: + IC(0.362 ns) + CELL(0.292 ns) = 17.055 ns; Loc. = LAB_X20_Y8; Fanout = 1; COMB Node = 'Mux52~209'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.654 ns" { Mux52~208 Mux52~209 } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 138 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.738 ns) 18.567 ns segdata\[3\]~reg0 24 REG LAB_X19_Y10 1 " "Info: 24: + IC(0.774 ns) + CELL(0.738 ns) = 18.567 ns; Loc. = LAB_X19_Y10; Fanout = 1; REG Node = 'segdata\[3\]~reg0'" { } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.512 ns" { Mux52~209 segdata[3]~reg0 } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 132 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.868 ns ( 47.76 % ) " "Info: Total cell delay = 8.868 ns ( 47.76 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.699 ns ( 52.24 % ) " "Info: Total interconnect delay = 9.699 ns ( 52.24 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "18.567 ns" { hour[4] lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[1]~COUTCOUT1 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~39 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~36COUT1 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~32COUT1 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~34COUT1 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~29 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[16]~38 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~48COUT1 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~50COUT1 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~46COUT1 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~43 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[23]~572 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_5|add_sub_cella[2]~48COUT1 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_5|add_sub_cella[2]~43 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[27]~568 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~48COUT1 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~50COUT1 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~43 lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[32]~567 Mux36~19 Mux52~208 Mux52~209 segdata[3]~reg0 } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "3 5 " "Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 5%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X14_Y0 X27_Y14 " "Info: The peak interconnect region extends from location X14_Y0 to location X27_Y14" { } { } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" { } { } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" { } { } 0 0 "Completed %1!s!" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "164 " "Info: Allocated 164 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 13 17:21:32 2007 " "Info: Processing ended: Fri Apr 13 17:21:32 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.fit.smsg " "Info: Generated suppressed messages file D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0}
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