elc_clock.merge.qmsg

verilog实践 elc_clock 电子时钟设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Partition Merge Quartus II " "Info: Running Quartus II Partition Merge" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 13 17:21:22 2007 " "Info: Processing started: Fri Apr 13 17:21:22 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_cdb --read_settings_files=off --write_settings_files=off elc_clock -c elc_clock --merge=on " "Info: Command: quartus_cdb --read_settings_files=off --write_settings_files=off elc_clock -c elc_clock --merge=on" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IAMERGE_PARTITION_SOURCE_SOURCE" "Top " "Info: Using synthesis netlist for partition \"Top\"" {  } {  } 0 0 "Using synthesis netlist for partition \"%1!s!\"" 0 0}
{ "Info" "IAMERGE_ATOM_BLACKBOX_RESOLVED" "1 1 " "Info: Netlist merging resolved 1 partition(s) out of the 1 partition(s) found" {  } {  } 0 0 "Netlist merging resolved %1!d! partition(s) out of the %2!d! partition(s) found" 0 0}
{ "Warning" "WAMERGE_UNNECESSARY_INPUT_PIN_HDR" "3 " "Warning: Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WAMERGE_UNNECESSARY_INPUT_PIN" "key0 " "Warning: No output dependent on input pin \"key0\"" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 8 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WAMERGE_UNNECESSARY_INPUT_PIN" "key1 " "Warning: No output dependent on input pin \"key1\"" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 8 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WAMERGE_UNNECESSARY_INPUT_PIN" "key2 " "Warning: No output dependent on input pin \"key2\"" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 8 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Partition Merge 0 s 4 s Quartus II " "Info: Quartus II Partition Merge was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "98 " "Info: Allocated 98 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 13 17:21:23 2007 " "Info: Processing ended: Fri Apr 13 17:21:23 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}