elc_clock.map.qmsg

verilog实践 elc_clock 电子时钟设计

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/61/quartus/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../altera/61/quartus/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" {  } { { "lpm_divide.tdf" "" { Text "d:/altera/61/quartus/libraries/megafunctions/lpm_divide.tdf" 118 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_divide:Mod0 " "Info: Elaborated megafunction instantiation \"lpm_divide:Mod0\"" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 141 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_htl.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_htl.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_htl " "Info: Found entity 1: lpm_divide_htl" {  } { { "db/lpm_divide_htl.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/lpm_divide_htl.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_akh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_akh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_akh " "Info: Found entity 1: sign_div_unsign_akh" {  } { { "db/sign_div_unsign_akh.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/sign_div_unsign_akh.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_4oe.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_4oe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_4oe " "Info: Found entity 1: alt_u_div_4oe" {  } { { "db/alt_u_div_4oe.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/alt_u_div_4oe.tdf" 32 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_3dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_3dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_3dc " "Info: Found entity 1: add_sub_3dc" {  } { { "db/add_sub_3dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_3dc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_4dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_4dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_4dc " "Info: Found entity 1: add_sub_4dc" {  } { { "db/add_sub_4dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_4dc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_5dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_5dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_5dc " "Info: Found entity 1: add_sub_5dc" {  } { { "db/add_sub_5dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_5dc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_6dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_6dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_6dc " "Info: Found entity 1: add_sub_6dc" {  } { { "db/add_sub_6dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_6dc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_7dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_7dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_7dc " "Info: Found entity 1: add_sub_7dc" {  } { { "db/add_sub_7dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_7dc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_59c.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_59c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_59c " "Info: Found entity 1: add_sub_59c" {  } { { "db/add_sub_59c.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_59c.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_divide:Div0 " "Info: Elaborated megafunction instantiation \"lpm_divide:Div0\"" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 146 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_e5m.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_e5m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_e5m " "Info: Found entity 1: lpm_divide_e5m" {  } { { "db/lpm_divide_e5m.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/lpm_divide_e5m.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "522 " "Info: Implemented 522 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "24 " "Info: Implemented 24 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "493 " "Info: Implemented 493 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "126 " "Info: Allocated 126 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 13 17:21:20 2007 " "Info: Processing ended: Fri Apr 13 17:21:20 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.map.smsg " "Info: Generated suppressed messages file D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}