elc_clock.map.qmsg

verilog实践 elc_clock 电子时钟设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 13 17:21:11 2007 " "Info: Processing started: Fri Apr 13 17:21:11 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off elc_clock -c elc_clock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off elc_clock -c elc_clock" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "elc_clock.v(47) " "Warning (10268): Verilog HDL information at elc_clock.v(47): Always Construct contains both blocking and non-blocking assignments" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 47 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "elc_clock.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file elc_clock.v" { { "Info" "ISGN_ENTITY_NAME" "1 elc_clock " "Info: Found entity 1: elc_clock" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "elc_clock " "Info: Elaborating entity \"elc_clock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "meun elc_clock.v(15) " "Warning (10036): Verilog HDL or VHDL warning at elc_clock.v(15): object \"meun\" assigned a value but never read" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 15 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "out_r1 elc_clock.v(17) " "Warning (10036): Verilog HDL or VHDL warning at elc_clock.v(17): object \"out_r1\" assigned a value but never read" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 17 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "out_r2 elc_clock.v(17) " "Warning (10036): Verilog HDL or VHDL warning at elc_clock.v(17): object \"out_r2\" assigned a value but never read" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 17 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 25 elc_clock.v(33) " "Warning (10230): Verilog HDL assignment warning at elc_clock.v(33): truncated value with size 32 to match size of target (25)" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 33 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 25 elc_clock.v(44) " "Warning (10230): Verilog HDL assignment warning at elc_clock.v(44): truncated value with size 32 to match size of target (25)" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 44 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 elc_clock.v(64) " "Warning (10230): Verilog HDL assignment warning at elc_clock.v(64): truncated value with size 32 to match size of target (7)" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 64 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 elc_clock.v(71) " "Warning (10230): Verilog HDL assignment warning at elc_clock.v(71): truncated value with size 32 to match size of target (7)" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 71 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 elc_clock.v(96) " "Warning (10230): Verilog HDL assignment warning at elc_clock.v(96): truncated value with size 32 to match size of target (7)" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 96 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 elc_clock.v(100) " "Warning (10230): Verilog HDL assignment warning at elc_clock.v(100): truncated value with size 32 to match size of target (7)" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 100 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 elc_clock.v(104) " "Warning (10230): Verilog HDL assignment warning at elc_clock.v(104): truncated value with size 32 to match size of target (7)" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 104 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 elc_clock.v(137) " "Warning (10230): Verilog HDL assignment warning at elc_clock.v(137): truncated value with size 32 to match size of target (4)" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 137 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "always4~2 always4~0 " "Info: Duplicate register \"always4~2\" merged to single register \"always4~0\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "always4~4 always4~0 " "Info: Duplicate register \"always4~4\" merged to single register \"always4~0\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "always4~6 always4~0 " "Info: Duplicate register \"always4~6\" merged to single register \"always4~0\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "always4~8 always4~0 " "Info: Duplicate register \"always4~8\" merged to single register \"always4~0\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "always4~10 always4~0 " "Info: Duplicate register \"always4~10\" merged to single register \"always4~0\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "always4~12 always4~0 " "Info: Duplicate register \"always4~12\" merged to single register \"always4~0\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "always4~14 always4~0 " "Info: Duplicate register \"always4~14\" merged to single register \"always4~0\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}