elc_clock.tan.qmsg

verilog实践 elc_clock 电子时钟设计

{ "Info" "ITDB_TH_RESULT" "second\[0\] reset clk -2.659 ns register " "Info: th for register \"second\[0\]\" (data pin = \"reset\", clock pin = \"clk\") is -2.659 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.034 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.034 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 52 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 52; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns clk1s 2 REG LC_X12_Y5_N3 22 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X12_Y5_N3; Fanout = 22; REG Node = 'clk1s'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk clk1s } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.369 ns) + CELL(0.711 ns) 8.034 ns second\[0\] 3 REG LC_X18_Y9_N1 12 " "Info: 3: + IC(4.369 ns) + CELL(0.711 ns) = 8.034 ns; Loc. = LC_X18_Y9_N1; Fanout = 12; REG Node = 'second\[0\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.080 ns" { clk1s second[0] } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 86 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.77 % ) " "Info: Total cell delay = 3.115 ns ( 38.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.919 ns ( 61.23 % ) " "Info: Total interconnect delay = 4.919 ns ( 61.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "8.034 ns" { clk clk1s second[0] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "8.034 ns" { clk clk~out0 clk1s second[0] } { 0.000ns 0.000ns 0.550ns 4.369ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 86 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.708 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.708 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns reset 1 PIN PIN_2 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 4; PIN Node = 'reset'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.291 ns) + CELL(0.114 ns) 8.874 ns second\[6\]~168 2 COMB LC_X17_Y9_N8 14 " "Info: 2: + IC(7.291 ns) + CELL(0.114 ns) = 8.874 ns; Loc. = LC_X17_Y9_N8; Fanout = 14; COMB Node = 'second\[6\]~168'"