elc_clock.tan.qmsg

verilog实践 elc_clock 电子时钟设计

{ "Info" "ITDB_TSU_RESULT" "minute\[0\] reset clk 3.340 ns register " "Info: tsu for register \"minute\[0\]\" (data pin = \"reset\", clock pin = \"clk\") is 3.340 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.337 ns + Longest pin register " "Info: + Longest pin to register delay is 11.337 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns reset 1 PIN PIN_2 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 4; PIN Node = 'reset'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.291 ns) + CELL(0.114 ns) 8.874 ns second\[6\]~168 2 COMB LC_X17_Y9_N8 14 " "Info: 2: + IC(7.291 ns) + CELL(0.114 ns) = 8.874 ns; Loc. = LC_X17_Y9_N8; Fanout = 14; COMB Node = 'second\[6\]~168'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.405 ns" { reset second[6]~168 } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 86 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.596 ns) + CELL(0.867 ns) 11.337 ns minute\[0\] 3 REG LC_X22_Y6_N1 12 " "Info: 3: + IC(1.596 ns) + CELL(0.867 ns) = 11.337 ns; Loc. = LC_X22_Y6_N1; Fanout = 12; REG Node = 'minute\[0\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.463 ns" { second[6]~168 minute[0] } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 86 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.450 ns ( 21.61 % ) " "Info: Total cell delay = 2.450 ns ( 21.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.887 ns ( 78.39 % ) " "Info: Total interconnect delay = 8.887 ns ( 78.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "11.337 ns" { reset second[6]~168 minute[0] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "11.337 ns" { reset reset~out0 second[6]~168 minute[0] } { 0.000ns 0.000ns 7.291ns 1.596ns } { 0.000ns 1.469ns 0.114ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 86 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.034 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 8.034 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 52 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 52; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns clk1s 2 REG LC_X12_Y5_N3 22 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X12_Y5_N3; Fanout = 22; REG Node = 'clk1s'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk clk1s } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.369 ns) + CELL(0.711 ns) 8.034 ns minute\[0\] 3 REG LC_X22_Y6_N1 12 " "Info: 3: + IC(4.369 ns) + CELL(0.711 ns) = 8.034 ns; Loc. = LC_X22_Y6_N1; Fanout = 12; REG Node = 'minute\[0\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.080 ns" { clk1s minute[0] } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 86 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.77 % ) " "Info: Total cell delay = 3.115 ns ( 38.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.919 ns ( 61.23 % ) " "Info: Total interconnect delay = 4.919 ns ( 61.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "8.034 ns" { clk clk1s minute[0] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "8.034 ns" { clk clk~out0 clk1s minute[0] } { 0.000ns 0.000ns 0.550ns 4.369ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "11.337 ns" { reset second[6]~168 minute[0] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "11.337 ns" { reset reset~out0 second[6]~168 minute[0] } { 0.000ns 0.000ns 7.291ns 1.596ns } { 0.000ns 1.469ns 0.114ns 0.867ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "8.034 ns" { clk clk1s minute[0] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "8.034 ns" { clk clk~out0 clk1s minute[0] } { 0.000ns 0.000ns 0.550ns 4.369ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk segdata\[7\] always4~0 12.598 ns register " "Info: tco from clock \"clk\" to destination pin \"segdata\[7\]\" through register \"always4~0\" is 12.598 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.174 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.174 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 52 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 52; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns clk1ms 2 REG LC_X8_Y6_N2 22 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N2; Fanout = 22; REG Node = 'clk1ms'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { clk clk1ms } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.499 ns) + CELL(0.711 ns) 7.174 ns always4~0 3 REG LC_X18_Y8_N1 8 " "Info: 3: + IC(3.499 ns) + CELL(0.711 ns) = 7.174 ns; Loc. = LC_X18_Y8_N1; Fanout = 8; REG Node = 'always4~0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.210 ns" { clk1ms always4~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 43.42 % ) " "Info: Total cell delay = 3.115 ns ( 43.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.059 ns ( 56.58 % ) " "Info: Total interconnect delay = 4.059 ns ( 56.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.174 ns" { clk clk1ms always4~0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.174 ns" { clk clk~out0 clk1ms always4~0 } { 0.000ns 0.000ns 0.560ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.200 ns + Longest register pin " "Info: + Longest register to pin delay is 5.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns always4~0 1 REG LC_X18_Y8_N1 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y8_N1; Fanout = 8; REG Node = 'always4~0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { always4~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.121 ns) + CELL(2.079 ns) 5.200 ns segdata\[7\] 2 PIN PIN_109 0 " "Info: 2: + IC(3.121 ns) + CELL(2.079 ns) = 5.200 ns; Loc. = PIN_109; Fanout = 0; PIN Node = 'segdata\[7\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.200 ns" { always4~0 segdata[7] } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 132 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.079 ns ( 39.98 % ) " "Info: Total cell delay = 2.079 ns ( 39.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.121 ns ( 60.02 % ) " "Info: Total interconnect delay = 3.121 ns ( 60.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.200 ns" { always4~0 segdata[7] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.200 ns" { always4~0 segdata[7] } { 0.000ns 3.121ns } { 0.000ns 2.079ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.174 ns" { clk clk1ms always4~0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.174 ns" { clk clk~out0 clk1ms always4~0 } { 0.000ns 0.000ns 0.560ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.200 ns" { always4~0 segdata[7] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.200 ns" { always4~0 segdata[7] } { 0.000ns 3.121ns } { 0.000ns 2.079ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}