📄 elc_clock.tan.qmsg

📁 verilog实践 elc_clock 电子时钟设计
💻 QMSG
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk1ms " "Info: Detected ripple clock \"clk1ms\" as buffer" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 11 -1 0 } } { "d:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1ms" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk1s " "Info: Detected ripple clock \"clk1s\" as buffer" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 11 -1 0 } } { "d:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1s" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register minute\[4\] register segdata\[3\]~reg0 49.18 MHz 20.335 ns Internal " "Info: Clock \"clk\" has Internal fmax of 49.18 MHz between source register \"minute\[4\]\" and destination register \"segdata\[3\]~reg0\" (period= 20.335 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "19.214 ns + Longest register register " "Info: + Longest register to register delay is 19.214 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns minute\[4\] 1 REG LC_X22_Y6_N5 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y6_N5; Fanout = 14; REG Node = 'minute\[4\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { minute[4] } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 86 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.520 ns) + CELL(0.432 ns) 0.952 ns lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[1\]~COUTCOUT1 2 COMB LC_X22_Y6_N8 1 " "Info: 2: + IC(0.520 ns) + CELL(0.432 ns) = 0.952 ns; Loc. = LC_X22_Y6_N8; Fanout = 1; COMB Node = 'lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[1\]~COUTCOUT1'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.952 ns" { minute[4] lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[1]~COUTCOUT1 } "NODE_NAME" } } { "db/add_sub_6dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_6dc.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 1.560 ns lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[2\]~47 3 COMB LC_X22_Y6_N9 2 " "Info: 3: + IC(0.000 ns) + CELL(0.608 ns) = 1.560 ns; Loc. = LC_X22_Y6_N9; Fanout = 2; COMB Node = 'lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[2\]~47'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.608 ns" { lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[1]~COUTCOUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~47 } "NODE_NAME" } } { "db/add_sub_6dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_6dc.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.189 ns) + CELL(0.432 ns) 3.181 ns lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[2\]~44COUT1 4 COMB LC_X21_Y5_N6 2 " "Info: 4: + IC(1.189 ns) + CELL(0.432 ns) = 3.181 ns; Loc. = LC_X21_Y5_N6; Fanout = 2; COMB Node = 'lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[2\]~44COUT1'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.621 ns" { lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~47 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~44COUT1 } "NODE_NAME" } } { "db/add_sub_6dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_6dc.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 3.261 ns lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[2\]~42COUT1 5 COMB LC_X21_Y5_N7 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 3.261 ns; Loc. = LC_X21_Y5_N7; Fanout = 2; COMB Node = 'lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[2\]~42COUT1'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~44COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~42COUT1 } "NODE_NAME" } } { "db/add_sub_6dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_6dc.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 3.341 ns lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[2\]~40COUT1 6 COMB LC_X21_Y5_N8 1 " "Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 3.341 ns; Loc. = LC_X21_Y5_N8; Fanout = 1; COMB Node = 'lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[2\]~40COUT1'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~42COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~40COUT1 } "NODE_NAME" } } { "db/add_sub_6dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_6dc.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 3.949 ns lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[2\]~37 7 COMB LC_X21_Y5_N9 17 " "Info: 7: + IC(0.000 ns) + CELL(0.608 ns) = 3.949 ns; Loc. = LC_X21_Y5_N9; Fanout = 17; COMB Node = 'lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_6dc:add_sub_3\|add_sub_cella\[2\]~37'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.608 ns" { lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~40COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~37 } "NODE_NAME" } } { "db/add_sub_6dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_6dc.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.833 ns) + CELL(0.114 ns) 4.896 ns lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|StageOut\[16\]~38 8 COMB LC_X22_Y5_N7 3 " "Info: 8: + IC(0.833 ns) + CELL(0.114 ns) = 4.896 ns; Loc. = LC_X22_Y5_N7; Fanout = 3; COMB Node = 'lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|StageOut\[16\]~38'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.947 ns" { lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~37 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[16]~38 } "NODE_NAME" } } { "db/alt_u_div_4oe.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/alt_u_div_4oe.tdf" 60 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.431 ns) + CELL(0.575 ns) 5.902 ns lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_4\|add_sub_cella\[2\]~52COUT1 9 COMB LC_X22_Y5_N1 2 " "Info: 9: + IC(0.431 ns) + CELL(0.575 ns) = 5.902 ns; Loc. = LC_X22_Y5_N1; Fanout = 2; COMB Node = 'lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_4\|add_sub_cella\[2\]~52COUT1'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.006 ns" { lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[16]~38 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~52COUT1 } "NODE_NAME" } } { "db/add_sub_7dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_7dc.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.982 ns lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_4\|add_sub_cella\[2\]~54COUT1 10 COMB LC_X22_Y5_N2 1 " "Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 5.982 ns; Loc. = LC_X22_Y5_N2; Fanout = 1; COMB Node = 'lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_4\|add_sub_cella\[2\]~54COUT1'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~52COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~54COUT1 } "NODE_NAME" } } { "db/add_sub_7dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_7dc.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 6.062 ns lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_4\|add_sub_cella\[2\]~50COUT1 11 COMB LC_X22_Y5_N3 1 " "Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 6.062 ns; Loc. = LC_X22_Y5_N3; Fanout = 1; COMB Node = 'lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_4\|add_sub_cella\[2\]~50COUT1'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~54COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~50COUT1 } "NODE_NAME" } } { "db/add_sub_7dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_7dc.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 6.670 ns lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_4\|add_sub_cella\[2\]~47 12 COMB LC_X22_Y5_N4 16 " "Info: 12: + IC(0.000 ns) + CELL(0.608 ns) = 6.670 ns; Loc. = LC_X22_Y5_N4; Fanout = 16; COMB Node = 'lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_4\|add_sub_cella\[2\]~47'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.608 ns" { lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~50COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~47 } "NODE_NAME" } } { "db/add_sub_7dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_7dc.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.802 ns) + CELL(0.114 ns) 7.586 ns lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|StageOut\[23\]~405 13 COMB LC_X21_Y5_N2 2 " "Info: 13: + IC(0.802 ns) + CELL(0.114 ns) = 7.586 ns; Loc. = LC_X21_Y5_N2; Fanout = 2; COMB Node = 'lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|StageOut\[23\]~405'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.916 ns" { lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~47 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[23]~405 } "NODE_NAME" } } { "db/alt_u_div_4oe.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/alt_u_div_4oe.tdf" 60 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.204 ns) + CELL(0.575 ns) 9.365 ns lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_5\|add_sub_cella\[2\]~50COUT1 14 COMB LC_X21_Y3_N8 1 " "Info: 14: + IC(1.204 ns) + CELL(0.575 ns) = 9.365 ns; Loc. = LC_X21_Y3_N8; Fanout = 1; COMB Node = 'lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_5\|add_sub_cella\[2\]~50COUT1'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.779 ns" { lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[23]~405 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_5|add_sub_cella[2]~50COUT1 } "NODE_NAME" } } { "db/add_sub_7dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_7dc.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 9.973 ns lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_5\|add_sub_cella\[2\]~47 15 COMB LC_X21_Y3_N9 16 " "Info: 15: + IC(0.000 ns) + CELL(0.608 ns) = 9.973 ns; Loc. = LC_X21_Y3_N9; Fanout = 16; COMB Node = 'lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_5\|add_sub_cella\[2\]~47'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.608 ns" { lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_5|add_sub_cella[2]~50COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_5|add_sub_cella[2]~47 } "NODE_NAME" } } { "db/add_sub_7dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_7dc.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.318 ns) + CELL(0.114 ns) 11.405 ns lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|StageOut\[26\]~13 16 COMB LC_X21_Y4_N4 2 " "Info: 16: + IC(1.318 ns) + CELL(0.114 ns) = 11.405 ns; Loc. = LC_X21_Y4_N4; Fanout = 2; COMB Node = 'lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|StageOut\[26\]~13'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.432 ns" { lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_5|add_sub_cella[2]~47 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[26]~13 } "NODE_NAME" } } { "db/alt_u_div_4oe.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/alt_u_div_4oe.tdf" 60 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.258 ns) + CELL(0.575 ns) 13.238 ns lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_6\|add_sub_cella\[2\]~54COUT1 17 COMB LC_X21_Y6_N1 1 " "Info: 17: + IC(1.258 ns) + CELL(0.575 ns) = 13.238 ns; Loc. = LC_X21_Y6_N1; Fanout = 1; COMB Node = 'lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_6\|add_sub_cella\[2\]~54COUT1'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.833 ns" { lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[26]~13 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~54COUT1 } "NODE_NAME" } } { "db/add_sub_7dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_7dc.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 13.318 ns lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_6\|add_sub_cella\[2\]~52COUT1 18 COMB LC_X21_Y6_N2 1 " "Info: 18: + IC(0.000 ns) + CELL(0.080 ns) = 13.318 ns; Loc. = LC_X21_Y6_N2; Fanout = 1; COMB Node = 'lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_6\|add_sub_cella\[2\]~52COUT1'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~54COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~52COUT1 } "NODE_NAME" } } { "db/add_sub_7dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_7dc.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 13.398 ns lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_6\|add_sub_cella\[2\]~50COUT1 19 COMB LC_X21_Y6_N3 1 " "Info: 19: + IC(0.000 ns) + CELL(0.080 ns) = 13.398 ns; Loc. = LC_X21_Y6_N3; Fanout = 1; COMB Node = 'lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_6\|add_sub_cella\[2\]~50COUT1'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~52COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~50COUT1 } "NODE_NAME" } } { "db/add_sub_7dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_7dc.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 14.006 ns lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_6\|add_sub_cella\[2\]~47 20 COMB LC_X21_Y6_N4 8 " "Info: 20: + IC(0.000 ns) + CELL(0.608 ns) = 14.006 ns; Loc. = LC_X21_Y6_N4; Fanout = 8; COMB Node = 'lpm_divide:Div1\|lpm_divide_e5m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_4oe:divider\|add_sub_7dc:add_sub_6\|add_sub_cella\[2\]~47'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.608 ns" { lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~50COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~47 } "NODE_NAME" } } { "db/add_sub_7dc.tdf" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/db/add_sub_7dc.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.482 ns) + CELL(0.292 ns) 14.780 ns Mux28~21 21 COMB LC_X21_Y6_N7 1 " "Info: 21: + IC(0.482 ns) + CELL(0.292 ns) = 14.780 ns; Loc. = LC_X21_Y6_N7; Fanout = 1; COMB Node = 'Mux28~21'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.774 ns" { lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~47 Mux28~21 } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 114 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.233 ns) + CELL(0.114 ns) 16.127 ns Mux52~207 22 COMB LC_X21_Y10_N8 1 " "Info: 22: + IC(1.233 ns) + CELL(0.114 ns) = 16.127 ns; Loc. = LC_X21_Y10_N8; Fanout = 1; COMB Node = 'Mux52~207'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.347 ns" { Mux28~21 Mux52~207 } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 138 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.244 ns) + CELL(0.292 ns) 17.663 ns Mux52~209 23 COMB LC_X20_Y8_N4 1 " "Info: 23: + IC(1.244 ns) + CELL(0.292 ns) = 17.663 ns; Loc. = LC_X20_Y8_N4; Fanout = 1; COMB Node = 'Mux52~209'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.536 ns" { Mux52~207 Mux52~209 } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 138 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.242 ns) + CELL(0.309 ns) 19.214 ns segdata\[3\]~reg0 24 REG LC_X19_Y10_N0 1 " "Info: 24: + IC(1.242 ns) + CELL(0.309 ns) = 19.214 ns; Loc. = LC_X19_Y10_N0; Fanout = 1; REG Node = 'segdata\[3\]~reg0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.551 ns" { Mux52~209 segdata[3]~reg0 } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 132 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.458 ns ( 38.82 % ) " "Info: Total cell delay = 7.458 ns ( 38.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.756 ns ( 61.18 % ) " "Info: Total interconnect delay = 11.756 ns ( 61.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "19.214 ns" { minute[4] lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[1]~COUTCOUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~47 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~44COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~42COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~40COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~37 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[16]~38 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~52COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~54COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~50COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~47 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[23]~405 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_5|add_sub_cella[2]~50COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_5|add_sub_cella[2]~47 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[26]~13 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~54COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~52COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~50COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~47 Mux28~21 Mux52~207 Mux52~209 segdata[3]~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "19.214 ns" { minute[4] lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[1]~COUTCOUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~47 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~44COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~42COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~40COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~37 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[16]~38 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~52COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~54COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~50COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~47 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[23]~405 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_5|add_sub_cella[2]~50COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_5|add_sub_cella[2]~47 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[26]~13 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~54COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~52COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~50COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~47 Mux28~21 Mux52~207 Mux52~209 segdata[3]~reg0 } { 0.000ns 0.520ns 0.000ns 1.189ns 0.000ns 0.000ns 0.000ns 0.833ns 0.431ns 0.000ns 0.000ns 0.000ns 0.802ns 1.204ns 0.000ns 1.318ns 1.258ns 0.000ns 0.000ns 0.000ns 0.482ns 1.233ns 1.244ns 1.242ns } { 0.000ns 0.432ns 0.608ns 0.432ns 0.080ns 0.080ns 0.608ns 0.114ns 0.575ns 0.080ns 0.080ns 0.608ns 0.114ns 0.575ns 0.608ns 0.114ns 0.575ns 0.080ns 0.080ns 0.608ns 0.292ns 0.114ns 0.292ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.860 ns - Smallest " "Info: - Smallest clock skew is -0.860 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.174 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.174 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 52 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 52; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns clk1ms 2 REG LC_X8_Y6_N2 22 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N2; Fanout = 22; REG Node = 'clk1ms'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { clk clk1ms } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.499 ns) + CELL(0.711 ns) 7.174 ns segdata\[3\]~reg0 3 REG LC_X19_Y10_N0 1 " "Info: 3: + IC(3.499 ns) + CELL(0.711 ns) = 7.174 ns; Loc. = LC_X19_Y10_N0; Fanout = 1; REG Node = 'segdata\[3\]~reg0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.210 ns" { clk1ms segdata[3]~reg0 } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 132 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 43.42 % ) " "Info: Total cell delay = 3.115 ns ( 43.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.059 ns ( 56.58 % ) " "Info: Total interconnect delay = 4.059 ns ( 56.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.174 ns" { clk clk1ms segdata[3]~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.174 ns" { clk clk~out0 clk1ms segdata[3]~reg0 } { 0.000ns 0.000ns 0.560ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.034 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.034 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 52 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 52; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns clk1s 2 REG LC_X12_Y5_N3 22 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X12_Y5_N3; Fanout = 22; REG Node = 'clk1s'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk clk1s } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.369 ns) + CELL(0.711 ns) 8.034 ns minute\[4\] 3 REG LC_X22_Y6_N5 14 " "Info: 3: + IC(4.369 ns) + CELL(0.711 ns) = 8.034 ns; Loc. = LC_X22_Y6_N5; Fanout = 14; REG Node = 'minute\[4\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.080 ns" { clk1s minute[4] } "NODE_NAME" } } { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 86 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.77 % ) " "Info: Total cell delay = 3.115 ns ( 38.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.919 ns ( 61.23 % ) " "Info: Total interconnect delay = 4.919 ns ( 61.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "8.034 ns" { clk clk1s minute[4] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "8.034 ns" { clk clk~out0 clk1s minute[4] } { 0.000ns 0.000ns 0.550ns 4.369ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.174 ns" { clk clk1ms segdata[3]~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.174 ns" { clk clk~out0 clk1ms segdata[3]~reg0 } { 0.000ns 0.000ns 0.560ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "8.034 ns" { clk clk1s minute[4] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "8.034 ns" { clk clk~out0 clk1s minute[4] } { 0.000ns 0.000ns 0.550ns 4.369ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 86 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "elc_clock.v" "" { Text "D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.v" 132 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "19.214 ns" { minute[4] lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[1]~COUTCOUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~47 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~44COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~42COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~40COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~37 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[16]~38 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~52COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~54COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~50COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~47 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[23]~405 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_5|add_sub_cella[2]~50COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_5|add_sub_cella[2]~47 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[26]~13 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~54COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~52COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~50COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~47 Mux28~21 Mux52~207 Mux52~209 segdata[3]~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "19.214 ns" { minute[4] lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[1]~COUTCOUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~47 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~44COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~42COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~40COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~37 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[16]~38 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~52COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~54COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~50COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~47 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[23]~405 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_5|add_sub_cella[2]~50COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_5|add_sub_cella[2]~47 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[26]~13 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~54COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~52COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~50COUT1 lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~47 Mux28~21 Mux52~207 Mux52~209 segdata[3]~reg0 } { 0.000ns 0.520ns 0.000ns 1.189ns 0.000ns 0.000ns 0.000ns 0.833ns 0.431ns 0.000ns 0.000ns 0.000ns 0.802ns 1.204ns 0.000ns 1.318ns 1.258ns 0.000ns 0.000ns 0.000ns 0.482ns 1.233ns 1.244ns 1.242ns } { 0.000ns 0.432ns 0.608ns 0.432ns 0.080ns 0.080ns 0.608ns 0.114ns 0.575ns 0.080ns 0.080ns 0.608ns 0.114ns 0.575ns 0.608ns 0.114ns 0.575ns 0.080ns 0.080ns 0.608ns 0.292ns 0.114ns 0.292ns 0.309ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.174 ns" { clk clk1ms segdata[3]~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.174 ns" { clk clk~out0 clk1ms segdata[3]~reg0 } { 0.000ns 0.000ns 0.560ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "8.034 ns" { clk clk1s minute[4] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "8.034 ns" { clk clk~out0 clk1s minute[4] } { 0.000ns 0.000ns 0.550ns 4.369ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
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