elc_clock.tan.rpt

来自「verilog实践 elc_clock 电子时钟设计」· RPT 代码 · 共 410 行 · 第 1/5 页

+-------+--------------+------------+-----------------+------------+------------+
; N/A   ; None         ; 12.598 ns  ; always4~0       ; segdata[7] ; clk        ;
; N/A   ; None         ; 12.598 ns  ; always4~0       ; segdata[6] ; clk        ;
; N/A   ; None         ; 12.536 ns  ; always4~0       ; segdata[5] ; clk        ;
; N/A   ; None         ; 12.536 ns  ; always4~0       ; segdata[4] ; clk        ;
; N/A   ; None         ; 11.985 ns  ; segdata[6]~reg0 ; segdata[6] ; clk        ;
; N/A   ; None         ; 11.931 ns  ; segdata[7]~reg0 ; segdata[7] ; clk        ;
; N/A   ; None         ; 11.892 ns  ; always4~0       ; segdata[3] ; clk        ;
; N/A   ; None         ; 11.892 ns  ; always4~0       ; segdata[2] ; clk        ;
; N/A   ; None         ; 11.849 ns  ; always4~0       ; segdata[1] ; clk        ;
; N/A   ; None         ; 11.849 ns  ; always4~0       ; segdata[0] ; clk        ;
; N/A   ; None         ; 11.795 ns  ; segcs[2]~reg0   ; segcs[2]   ; clk        ;
; N/A   ; None         ; 11.730 ns  ; segdata[4]~reg0 ; segdata[4] ; clk        ;
; N/A   ; None         ; 11.686 ns  ; segcs[0]~reg0   ; segcs[0]   ; clk        ;
; N/A   ; None         ; 11.678 ns  ; segcs[1]~reg0   ; segcs[1]   ; clk        ;
; N/A   ; None         ; 11.666 ns  ; segcs[5]~reg0   ; segcs[5]   ; clk        ;
; N/A   ; None         ; 11.662 ns  ; segdata[3]~reg0 ; segdata[3] ; clk        ;
; N/A   ; None         ; 11.286 ns  ; segdata[0]~reg0 ; segdata[0] ; clk        ;
; N/A   ; None         ; 11.284 ns  ; segdata[2]~reg0 ; segdata[2] ; clk        ;
; N/A   ; None         ; 11.276 ns  ; segdata[1]~reg0 ; segdata[1] ; clk        ;
; N/A   ; None         ; 11.248 ns  ; segdata[5]~reg0 ; segdata[5] ; clk        ;
; N/A   ; None         ; 11.121 ns  ; segcs[3]~reg0   ; segcs[3]   ; clk        ;
; N/A   ; None         ; 11.116 ns  ; segcs[4]~reg0   ; segcs[4]   ; clk        ;
; N/A   ; None         ; 10.804 ns  ; segcs[7]~reg0   ; segcs[7]   ; clk        ;
; N/A   ; None         ; 10.803 ns  ; segcs[6]~reg0   ; segcs[6]   ; clk        ;
+-------+--------------+------------+-----------------+------------+------------+


+------------------------------------------------------------------------+
; th                                                                     ;
+---------------+-------------+-----------+-------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To        ; To Clock ;
+---------------+-------------+-----------+-------+-----------+----------+
; N/A           ; None        ; -2.659 ns ; reset ; second[0] ; clk      ;
; N/A           ; None        ; -2.659 ns ; reset ; second[1] ; clk      ;
; N/A           ; None        ; -2.659 ns ; reset ; second[2] ; clk      ;
; N/A           ; None        ; -2.659 ns ; reset ; second[3] ; clk      ;
; N/A           ; None        ; -2.659 ns ; reset ; second[5] ; clk      ;
; N/A           ; None        ; -2.659 ns ; reset ; second[4] ; clk      ;
; N/A           ; None        ; -2.659 ns ; reset ; second[6] ; clk      ;
; N/A           ; None        ; -3.036 ns ; reset ; hour[0]   ; clk      ;
; N/A           ; None        ; -3.036 ns ; reset ; hour[1]   ; clk      ;
; N/A           ; None        ; -3.036 ns ; reset ; hour[6]   ; clk      ;
; N/A           ; None        ; -3.036 ns ; reset ; hour[2]   ; clk      ;
; N/A           ; None        ; -3.036 ns ; reset ; hour[3]   ; clk      ;
; N/A           ; None        ; -3.036 ns ; reset ; hour[5]   ; clk      ;
; N/A           ; None        ; -3.036 ns ; reset ; hour[4]   ; clk      ;
; N/A           ; None        ; -3.116 ns ; reset ; minute[0] ; clk      ;
; N/A           ; None        ; -3.116 ns ; reset ; minute[1] ; clk      ;
; N/A           ; None        ; -3.116 ns ; reset ; minute[2] ; clk      ;
; N/A           ; None        ; -3.116 ns ; reset ; minute[3] ; clk      ;
; N/A           ; None        ; -3.116 ns ; reset ; minute[6] ; clk      ;
; N/A           ; None        ; -3.116 ns ; reset ; minute[5] ; clk      ;
; N/A           ; None        ; -3.116 ns ; reset ; minute[4] ; clk      ;
+---------------+-------------+-----------+-------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Fri Apr 13 17:21:43 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off elc_clock -c elc_clock --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "clk1ms" as buffer
    Info: Detected ripple clock "clk1s" as buffer
Info: Clock "clk" has Internal fmax of 49.18 MHz between source register "minute[4]" and destination register "segdata[3]~reg0" (period= 20.335 ns)
    Info: + Longest register to register delay is 19.214 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y6_N5; Fanout = 14; REG Node = 'minute[4]'
        Info: 2: + IC(0.520 ns) + CELL(0.432 ns) = 0.952 ns; Loc. = LC_X22_Y6_N8; Fanout = 1; COMB Node = 'lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[1]~COUTCOUT1'
        Info: 3: + IC(0.000 ns) + CELL(0.608 ns) = 1.560 ns; Loc. = LC_X22_Y6_N9; Fanout = 2; COMB Node = 'lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~47'
        Info: 4: + IC(1.189 ns) + CELL(0.432 ns) = 3.181 ns; Loc. = LC_X21_Y5_N6; Fanout = 2; COMB Node = 'lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~44COUT1'
        Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 3.261 ns; Loc. = LC_X21_Y5_N7; Fanout = 2; COMB Node = 'lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~42COUT1'
        Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 3.341 ns; Loc. = LC_X21_Y5_N8; Fanout = 1; COMB Node = 'lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~40COUT1'
        Info: 7: + IC(0.000 ns) + CELL(0.608 ns) = 3.949 ns; Loc. = LC_X21_Y5_N9; Fanout = 17; COMB Node = 'lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~37'
        Info: 8: + IC(0.833 ns) + CELL(0.114 ns) = 4.896 ns; Loc. = LC_X22_Y5_N7; Fanout = 3; COMB Node = 'lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[16]~38'
        Info: 9: + IC(0.431 ns) + CELL(0.575 ns) = 5.902 ns; Loc. = LC_X22_Y5_N1; Fanout = 2; COMB Node = 'lpm_divide:Div1|lpm_divide_e5m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~52COUT1'
        Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 5.982 ns; Loc. = LC_X22_Y5_N2; Fanout = 1; COMB Node = 'lpm_divide:Div1|lpm_div