elc_clock.fit.smsg

verilog实践 elc_clock 电子时钟设计

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Fri Apr 13 17:21:24 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off elc_clock -c elc_clock
Info: Selected device EP1C3T144C8 for design "elc_clock"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 514 of 514 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C6T144C8 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 12
    Info: Pin ~ASDO~ is reserved at location 25
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "clk" to use Global clock in PIN 16
Info: Automatically promoted some destinations of signal "clk1ms" to use Global clock
    Info: Destination "clk1ms" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "clk1s" to use Global clock
    Info: Destination "clk1s" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 18.567 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X23_Y11; Fanout = 14; REG Node = 'hour[4]'
    Info: 2: + IC(1.153 ns) + CELL(0.575 ns) = 1.728 ns; Loc. = LAB_X22_Y10; Fanout = 1; COMB Node = 'lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[1]~COUTCOUT1'
    Info: 3: + IC(0.000 ns) + CELL(0.608 ns) = 2.336 ns; Loc. = LAB_X22_Y10; Fanout = 2; COMB Node = 'lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~39'
    Info: 4: + IC(0.385 ns) + CELL(0.575 ns) = 3.296 ns; Loc. = LAB_X22_Y10; Fanout = 2; COMB Node = 'lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~36COUT1'
    Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 3.376 ns; Loc. = LAB_X22_Y10; Fanout = 2; COMB Node = 'lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~32COUT1'
    Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 3.456 ns; Loc. = LAB_X22_Y10; Fanout = 1; COMB Node = 'lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~34COUT1'
    Info: 7: + IC(0.000 ns) + CELL(0.608 ns) = 4.064 ns; Loc. = LAB_X22_Y10; Fanout = 8; COMB Node = 'lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_6dc:add_sub_3|add_sub_cella[2]~29'
    Info: 8: + IC(0.303 ns) + CELL(0.590 ns) = 4.957 ns; Loc. = LAB_X23_Y10; Fanout = 3; COMB Node = 'lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[16]~38'
    Info: 9: + IC(0.533 ns) + CELL(0.432 ns) = 5.922 ns; Loc. = LAB_X23_Y10; Fanout = 2; COMB Node = 'lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~48COUT1'
    Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 6.002 ns; Loc. = LAB_X23_Y10; Fanout = 1; COMB Node = 'lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~50COUT1'
    Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 6.082 ns; Loc. = LAB_X23_Y10; Fanout = 1; COMB Node = 'lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~46COUT1'
    Info: 12: + IC(0.000 ns) + CELL(0.608 ns) = 6.690 ns; Loc. = LAB_X23_Y10; Fanout = 8; COMB Node = 'lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_4|add_sub_cella[2]~43'
    Info: 13: + IC(0.779 ns) + CELL(0.114 ns) = 7.583 ns; Loc. = LAB_X22_Y10; Fanout = 2; COMB Node = 'lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[23]~572'
    Info: 14: + IC(1.077 ns) + CELL(0.575 ns) = 9.235 ns; Loc. = LAB_X22_Y9; Fanout = 1; COMB Node = 'lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_5|add_sub_cella[2]~48COUT1'
    Info: 15: + IC(0.000 ns) + CELL(0.608 ns) = 9.843 ns; Loc. = LAB_X22_Y9; Fanout = 6; COMB Node = 'lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_5|add_sub_cella[2]~43'
    Info: 16: + IC(1.250 ns) + CELL(0.114 ns) = 11.207 ns; Loc. = LAB_X23_Y11; Fanout = 4; COMB Node = 'lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[27]~568'
    Info: 17: + IC(1.007 ns) + CELL(0.575 ns) = 12.789 ns; Loc. = LAB_X20_Y11; Fanout = 1; COMB Node = 'lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~48COUT1'
    Info: 18: + IC(0.000 ns) + CELL(0.080 ns) = 12.869 ns; Loc. = LAB_X20_Y11; Fanout = 1; COMB Node = 'lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~50COUT1'
    Info: 19: + IC(0.000 ns) + CELL(0.608 ns) = 13.477 ns; Loc. = LAB_X20_Y11; Fanout = 4; COMB Node = 'lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|add_sub_7dc:add_sub_6|add_sub_cella[2]~43'
    Info: 20: + IC(0.779 ns) + CELL(0.114 ns) = 14.370 ns; Loc. = LAB_X19_Y11; Fanout = 8; COMB Node = 'lpm_divide:Mod2|lpm_divide_htl:auto_generated|sign_div_unsign_akh:divider|alt_u_div_4oe:divider|StageOut[32]~567'
    Info: 21: + IC(1.085 ns) + CELL(0.292 ns) = 15.747 ns; Loc. = LAB_X20_Y8; Fanout = 1; COMB Node = 'Mux36~19'
    Info: 22: + IC(0.212 ns) + CELL(0.442 ns) = 16.401 ns; Loc. = LAB_X20_Y8; Fanout = 1; COMB Node = 'Mux52~208'
    Info: 23: + IC(0.362 ns) + CELL(0.292 ns) = 17.055 ns; Loc. = LAB_X20_Y8; Fanout = 1; COMB Node = 'Mux52~209'
    Info: 24: + IC(0.774 ns) + CELL(0.738 ns) = 18.567 ns; Loc. = LAB_X19_Y10; Fanout = 1; REG Node = 'segdata[3]~reg0'
    Info: Total cell delay = 8.868 ns ( 47.76 % )
    Info: Total interconnect delay = 9.699 ns ( 52.24 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 5%
    Info: The peak interconnect region extends from location X14_Y0 to location X27_Y14
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Allocated 164 megabytes of memory during processing
    Info: Processing ended: Fri Apr 13 17:21:32 2007
    Info: Elapsed time: 00:00:08