elc_clock.map.rpt

verilog实践 elc_clock 电子时钟设计

; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE           ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE         ;
+------------------------+----------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_divide:Mod2 ;
+------------------------+----------------+------------------------+
; Parameter Name         ; Value          ; Type                   ;
+------------------------+----------------+------------------------+
; LPM_WIDTHN             ; 7              ; Untyped                ;
; LPM_WIDTHD             ; 4              ; Untyped                ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_PIPELINE           ; 0              ; Untyped                ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                ;
; CBXI_PARAMETER         ; lpm_divide_htl ; Untyped                ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY             ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY           ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE           ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE         ;
+------------------------+----------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_divide:Div2 ;
+------------------------+----------------+------------------------+
; Parameter Name         ; Value          ; Type                   ;
+------------------------+----------------+------------------------+
; LPM_WIDTHN             ; 7              ; Untyped                ;
; LPM_WIDTHD             ; 4              ; Untyped                ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_PIPELINE           ; 0              ; Untyped                ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                ;
; CBXI_PARAMETER         ; lpm_divide_e5m ; Untyped                ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY             ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY           ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE           ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE         ;
+------------------------+----------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Fri Apr 13 17:21:11 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off elc_clock -c elc_clock
Info: Found 1 design units, including 1 entities, in source file elc_clock.v
    Info: Found entity 1: elc_clock
Info: Elaborating entity "elc_clock" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at elc_clock.v(15): object "meun" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at elc_clock.v(17): object "out_r1" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at elc_clock.v(17): object "out_r2" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at elc_clock.v(33): truncated value with size 32 to match size of target (25)
Warning (10230): Verilog HDL assignment warning at elc_clock.v(44): truncated value with size 32 to match size of target (25)
Warning (10230): Verilog HDL assignment warning at elc_clock.v(64): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at elc_clock.v(71): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at elc_clock.v(96): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at elc_clock.v(100): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at elc_clock.v(104): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at elc_clock.v(137): truncated value with size 32 to match size of target (4)
Info: Duplicate registers merged to single register
    Info: Duplicate register "always4~2" merged to single register "always4~0"
    Info: Duplicate register "always4~4" merged to single register "always4~0"
    Info: Duplicate register "always4~6" merged to single register "always4~0"
    Info: Duplicate register "always4~8" merged to single register "always4~0"
    Info: Duplicate register "always4~10" merged to single register "always4~0"
    Info: Duplicate register "always4~12" merged to single register "always4~0"
    Info: Duplicate register "always4~14" merged to single register "always4~0"
Info: Found 1 design units, including 1 entities, in source file ../../../../altera/61/quartus/libraries/megafunctions/lpm_divide.tdf
    Info: Found entity 1: lpm_divide
Info: Elaborated megafunction instantiation "lpm_divide:Mod0"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_htl.tdf
    Info: Found entity 1: lpm_divide_htl
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_akh.tdf
    Info: Found entity 1: sign_div_unsign_akh
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_4oe.tdf
    Info: Found entity 1: alt_u_div_4oe
Info: Found 1 design units, including 1 entities, in source file db/add_sub_3dc.tdf
    Info: Found entity 1: add_sub_3dc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_4dc.tdf
    Info: Found entity 1: add_sub_4dc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_5dc.tdf
    Info: Found entity 1: add_sub_5dc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_6dc.tdf
    Info: Found entity 1: add_sub_6dc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_7dc.tdf
    Info: Found entity 1: add_sub_7dc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_59c.tdf
    Info: Found entity 1: add_sub_59c
Info: Elaborated megafunction instantiation "lpm_divide:Div0"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_e5m.tdf
    Info: Found entity 1: lpm_divide_e5m
Info: Implemented 522 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 24 output pins
    Info: Implemented 493 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings
    Info: Allocated 126 megabytes of memory during processing
    Info: Processing ended: Fri Apr 13 17:21:20 2007
    Info: Elapsed time: 00:00:09


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in D:/毕业设计文件/实习训练/Verilog实践/电子时钟/elc_clock.map.smsg.