elc_clock.map.summary

来自「verilog实践 elc_clock 电子时钟设计」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Fri Apr 13 17:21:20 2007
Quartus II Version : 6.1 Build 201 11/27/2006 SJ Full Version
Revision Name : elc_clock
Top-level Entity Name : elc_clock
Family : Cyclone
Total logic elements : N/A until Partition Merge
Total pins : N/A until Partition Merge
Total virtual pins : N/A until Partition Merge
Total memory bits : N/A until Partition Merge
Total PLLs : N/A until Partition Merge