colorbar.vo

VGA的verilog hdl 程序

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version"

// DATE "10/25/2008 17:44:39"

// 
// Device: Altera EP2C35F484C8 Package FBGA484
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module 	ColorBar (
	rst,
	clk,
	altera_reserved_tms,
	altera_reserved_tck,
	altera_reserved_tdi,
	VGA_HS,
	VGA_VS,
	VGA_BLANK,
	VGA_CLK,
	RGB,
	VGA_RGB,
	altera_reserved_tdo);
input 	rst;
input 	clk;
input 	altera_reserved_tms;
input 	altera_reserved_tck;
input 	altera_reserved_tdi;
output 	VGA_HS;
output 	VGA_VS;
output 	VGA_BLANK;
output 	VGA_CLK;
output 	[12:0] RGB;
output 	[2:0] VGA_RGB;
output 	altera_reserved_tdo;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("ColorBar_v.sdo");
// synopsys translate_on

wire \inst4|altpll_component|_clk1 ;
wire \inst4|altpll_component|_clk2 ;
wire \inst|vcnt[4] ;
wire \altera_internal_jtag~TCKUTAP ;
wire \inst|always1~295 ;
wire \inst|always1~296 ;
wire \inst|vcnt[4]~251 ;
wire \inst|LessThan~986 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[0] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[0] ;
wire \sld_hub_inst|hub_tdo~279 ;
wire \sld_hub_inst|hub_tdo~280 ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR[0] ;
wire \sld_hub_inst|hub_tdo~281 ;
wire \sld_hub_inst|instruction_decoder|auto_generated|dffe1a[2] ;
wire \sld_hub_inst|IRF_ENABLE[1]~76 ;
wire \sld_hub_inst|reduce_nor~56 ;
wire \sld_hub_inst|IRSR|Q[2] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[1] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|_~1313 ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[1] ;
wire \sld_hub_inst|instruction_decoder|auto_generated|dffe1a[3] ;
wire \sld_hub_inst|IRSR|Q[0]~117 ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[1] ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[3] ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[2] ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR~386 ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[0] ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR~387 ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR[1] ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR~388 ;
wire \auto_signaltap_0|comb~26 ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1|match_out ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|match_out ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|match_out ;
wire \auto_signaltap_0|ela_control|ela_level_seq_mgr|trigger_happened~115 ;
wire \sld_hub_inst|instruction_decoder|auto_generated|w_anode28w[3] ;
wire \sld_hub_inst|jtag_state_machine|tms_cnt[2] ;
wire \sld_hub_inst|jtag_state_machine|tms_cnt[0] ;
wire \sld_hub_inst|jtag_state_machine|tms_cnt[1] ;
wire \sld_hub_inst|jtag_state_machine|state~444 ;
wire \auto_signaltap_0|ela_control|sm2|status_out[2] ;
wire \sld_hub_inst|IRSR_D[2]~405 ;
wire \auto_signaltap_0|ela_control|sm1|ela_done ;
wire \sld_hub_inst|IRSR_D[2]~406 ;
wire \sld_hub_inst|IRSR_D[2]~407 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[2] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|_~1314 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[10] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[8] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[6] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[4] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[3] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[1] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_comb_bita1 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_comb_bita3 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_comb_bita4 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_comb_bita6 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_comb_bita8 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_comb_bita10 ;
wire \auto_signaltap_0|ela_control|sm1|edq~69 ;
wire \sld_hub_inst|instruction_decoder|auto_generated|w_anode38w[3] ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[1]~209 ;
wire \auto_signaltap_0|crc_rom_sr|word_counter~210 ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[0]~6 ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[2]~211 ;
wire \auto_signaltap_0|crc_rom_sr|reduce_nor~3 ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[0]~212 ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR[2] ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR~389 ;
wire \sld_hub_inst|jtag_state_machine|state[14] ;
wire \auto_signaltap_0|acq_trigger_in_reg[5] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1|holdff ;
wire \auto_signaltap_0|acq_trigger_in_reg[0] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|holdff ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|holdff ;
wire \sld_hub_inst|jtag_state_machine|tms_cnt~4 ;
wire \sld_hub_inst|jtag_state_machine|tms_cnt~0 ;
wire \sld_hub_inst|jtag_state_machine|tms_cnt~1 ;
wire \auto_signaltap_0|ela_control|sm1|edq~70 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[3] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|_~1315 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|pre_hazard[7] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|pre_hazard[5] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|pre_hazard[4] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|pre_hazard[2] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_comb_bita2 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_comb_bita4 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_comb_bita5 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_comb_bita7 ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR[3] ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR~390 ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR~391 ;
wire \sld_hub_inst|jtag_state_machine|state[13] ;
wire \sld_hub_inst|jtag_state_machine|state~28 ;
wire \auto_signaltap_0|ela_control|\trigger_in_trigger_module_enabled_gen:trigger_in_match|\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|holdff ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[4] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|_~1316 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[10] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[6] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_compare|comparator|cmp_end|comp|sub_comptree|sub_comptree|cmp_end|aeb_out~78 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[2] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[0] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_compare|comparator|cmp_end|comp|sub_comptree|sub_comptree|cmp_end|aeb_out~79 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[9] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[3] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_compare|comparator|cmp_end|comp|sub_comptree|sub_comptree|cmp_end|aeb_out~80 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[4] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[1] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_compare|comparator|cmp_end|comp|sub_comptree|sub_comptree|cmp_end|aeb_out~81 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_compare|comparator|cmp_end|comp|sub_comptree|sub_comptree|cmp_end|aeb_out~82 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[7] ;