📄 prev_cmp_timer.tan.qmsg
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{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLSec\[0\] " "Warning: Node \"DLED:U2\|oLSec\[0\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 113 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLSec\[1\] " "Warning: Node \"DLED:U2\|oLSec\[1\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 113 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLSec\[2\] " "Warning: Node \"DLED:U2\|oLSec\[2\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 113 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLSec\[3\] " "Warning: Node \"DLED:U2\|oLSec\[3\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 113 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLSec\[4\] " "Warning: Node \"DLED:U2\|oLSec\[4\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 113 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLSec\[5\] " "Warning: Node \"DLED:U2\|oLSec\[5\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 113 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLSec\[6\] " "Warning: Node \"DLED:U2\|oLSec\[6\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 113 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLSec\[7\] " "Warning: Node \"DLED:U2\|oLSec\[7\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 113 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLSec\[8\] " "Warning: Node \"DLED:U2\|oLSec\[8\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 113 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLSec\[9\] " "Warning: Node \"DLED:U2\|oLSec\[9\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 113 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLSec\[11\] " "Warning: Node \"DLED:U2\|oLSec\[11\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 113 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLSec\[12\] " "Warning: Node \"DLED:U2\|oLSec\[12\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 113 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLSec\[13\] " "Warning: Node \"DLED:U2\|oLSec\[13\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 113 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLMin\[0\] " "Warning: Node \"DLED:U2\|oLMin\[0\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 47 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLMin\[1\] " "Warning: Node \"DLED:U2\|oLMin\[1\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 47 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLMin\[2\] " "Warning: Node \"DLED:U2\|oLMin\[2\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 47 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLMin\[3\] " "Warning: Node \"DLED:U2\|oLMin\[3\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 47 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLMin\[4\] " "Warning: Node \"DLED:U2\|oLMin\[4\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 47 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLMin\[5\] " "Warning: Node \"DLED:U2\|oLMin\[5\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 47 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLMin\[6\] " "Warning: Node \"DLED:U2\|oLMin\[6\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 47 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLMin\[7\] " "Warning: Node \"DLED:U2\|oLMin\[7\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 47 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLMin\[8\] " "Warning: Node \"DLED:U2\|oLMin\[8\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 47 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLMin\[9\] " "Warning: Node \"DLED:U2\|oLMin\[9\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 47 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLMin\[11\] " "Warning: Node \"DLED:U2\|oLMin\[11\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 47 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLMin\[12\] " "Warning: Node \"DLED:U2\|oLMin\[12\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 47 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLMin\[13\] " "Warning: Node \"DLED:U2\|oLMin\[13\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 47 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLHou\[0\] " "Warning: Node \"DLED:U2\|oLHou\[0\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 17 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLHou\[1\] " "Warning: Node \"DLED:U2\|oLHou\[1\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 17 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLHou\[2\] " "Warning: Node \"DLED:U2\|oLHou\[2\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 17 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLHou\[3\] " "Warning: Node \"DLED:U2\|oLHou\[3\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 17 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLHou\[4\] " "Warning: Node \"DLED:U2\|oLHou\[4\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 17 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLHou\[5\] " "Warning: Node \"DLED:U2\|oLHou\[5\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 17 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLHou\[6\] " "Warning: Node \"DLED:U2\|oLHou\[6\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 17 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLHou\[7\] " "Warning: Node \"DLED:U2\|oLHou\[7\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 17 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLHou\[9\] " "Warning: Node \"DLED:U2\|oLHou\[9\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 17 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLHou\[12\] " "Warning: Node \"DLED:U2\|oLHou\[12\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 17 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DLED:U2\|oLHou\[13\] " "Warning: Node \"DLED:U2\|oLHou\[13\]\" is a latch" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 17 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "FTIMER:U3\|oHouR " "Warning: Node \"FTIMER:U3\|oHouR\" is a latch" { } { { "FTIMER.vhd" "" { Text "D:/timer/FTIMER.vhd" 12 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "FTIMER:U3\|\\SR:Ring " "Warning: Node \"FTIMER:U3\|\\SR:Ring\" is a latch" { } { } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} } { } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "iclk " "Info: Assuming node \"iclk\" is an undefined clock" { } { { "TIMER.vhd" "" { Text "D:/timer/TIMER.vhd" 6 -1 0 } } { "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "iclk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "13 " "Warning: Found 13 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "DLED:U2\|Mux41~23 " "Info: Detected gated clock \"DLED:U2\|Mux41~23\" as buffer" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 19 -1 0 } } { "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "DLED:U2\|Mux41~23" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DTIMER:U1\|\\F:hou\[3\] " "Info: Detected ripple clock \"DTIMER:U1\|\\F:hou\[3\]\" as buffer" { } { { "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "DTIMER:U1\|\\F:hou\[3\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DTIMER:U1\|\\F:hou\[4\] " "Info: Detected ripple clock \"DTIMER:U1\|\\F:hou\[4\]\" as buffer" { } { { "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "DTIMER:U1\|\\F:hou\[4\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "DLED:U2\|Mux23~52 " "Info: Detected gated clock \"DLED:U2\|Mux23~52\" as buffer" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 49 -1 0 } } { "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "DLED:U2\|Mux23~52" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DTIMER:U1\|\\F:min\[4\] " "Info: Detected ripple clock \"DTIMER:U1\|\\F:min\[4\]\" as buffer" { } { { "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "DTIMER:U1\|\\F:min\[4\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DTIMER:U1\|\\F:min\[5\] " "Info: Detected ripple clock \"DTIMER:U1\|\\F:min\[5\]\" as buffer" { } { { "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "DTIMER:U1\|\\F:min\[5\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DTIMER:U1\|\\F:min\[2\] " "Info: Detected ripple clock \"DTIMER:U1\|\\F:min\[2\]\" as buffer" { } { { "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "DTIMER:U1\|\\F:min\[2\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DTIMER:U1\|\\F:min\[3\] " "Info: Detected ripple clock \"DTIMER:U1\|\\F:min\[3\]\" as buffer" { } { { "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "DTIMER:U1\|\\F:min\[3\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "DLED:U2\|Mux7~52 " "Info: Detected gated clock \"DLED:U2\|Mux7~52\" as buffer" { } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 115 -1 0 } } { "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "DLED:U2\|Mux7~52" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DTIMER:U1\|\\F:sec\[5\] " "Info: Detected ripple clock \"DTIMER:U1\|\\F:sec\[5\]\" as buffer" { } { { "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "DTIMER:U1\|\\F:sec\[5\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DTIMER:U1\|\\F:sec\[4\] " "Info: Detected ripple clock \"DTIMER:U1\|\\F:sec\[4\]\" as buffer" { } { { "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "DTIMER:U1\|\\F:sec\[4\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DTIMER:U1\|\\F:sec\[2\] " "Info: Detected ripple clock \"DTIMER:U1\|\\F:sec\[2\]\" as buffer" { } { { "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "DTIMER:U1\|\\F:sec\[2\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DTIMER:U1\|\\F:sec\[3\] " "Info: Detected ripple clock \"DTIMER:U1\|\\F:sec\[3\]\" as buffer" { } { { "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "DTIMER:U1\|\\F:sec\[3\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
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