📄 timer.map.rpt
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+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements ; 230 ;
; ; ;
; Total combinational functions ; 230 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 115 ;
; -- 3 input functions ; 59 ;
; -- <=2 input functions ; 56 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 205 ;
; -- arithmetic mode ; 25 ;
; ; ;
; Total registers ; 43 ;
; -- Dedicated logic registers ; 43 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 58 ;
; Maximum fan-out node ; iclk ;
; Maximum fan-out ; 43 ;
; Total fan-out ; 934 ;
; Average fan-out ; 2.82 ;
+---------------------------------------------+-------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |TIMER ; 230 (0) ; 43 (0) ; 0 ; 0 ; 0 ; 0 ; 58 ; 0 ; |TIMER ; work ;
; |DLED:U2| ; 137 (137) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TIMER|DLED:U2 ; work ;
; |DTIMER:U1| ; 79 (79) ; 43 (43) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TIMER|DTIMER:U1 ; work ;
; |FTIMER:U3| ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |TIMER|FTIMER:U3 ; work ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-----------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+-----------------------------------------------------+----------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+-----------------------------------------------------+----------------------+------------------------+
; DLED:U2|oLSec[0] ; DLED:U2|Mux7 ; yes ;
; DLED:U2|oLSec[1] ; DLED:U2|Mux7 ; yes ;
; DLED:U2|oLSec[2] ; DLED:U2|Mux7 ; yes ;
; DLED:U2|oLSec[3] ; DLED:U2|Mux7 ; yes ;
; DLED:U2|oLSec[4] ; DLED:U2|Mux7 ; yes ;
; DLED:U2|oLSec[5] ; DLED:U2|Mux7 ; yes ;
; DLED:U2|oLSec[6] ; DLED:U2|Mux7 ; yes ;
; DLED:U2|oLSec[7] ; DLED:U2|Mux7 ; yes ;
; DLED:U2|oLSec[8] ; DLED:U2|Mux7 ; yes ;
; DLED:U2|oLSec[9] ; DLED:U2|Mux7 ; yes ;
; DLED:U2|oLSec[10] ; DLED:U2|Mux7 ; yes ;
; DLED:U2|oLSec[11] ; DLED:U2|Mux7 ; yes ;
; DLED:U2|oLSec[12] ; DLED:U2|Mux7 ; yes ;
; DLED:U2|oLSec[13] ; DLED:U2|Mux7 ; yes ;
; DLED:U2|oLMin[0] ; DLED:U2|Mux23 ; yes ;
; DLED:U2|oLMin[1] ; DLED:U2|Mux23 ; yes ;
; DLED:U2|oLMin[2] ; DLED:U2|Mux23 ; yes ;
; DLED:U2|oLMin[3] ; DLED:U2|Mux23 ; yes ;
; DLED:U2|oLMin[4] ; DLED:U2|Mux23 ; yes ;
; DLED:U2|oLMin[5] ; DLED:U2|Mux23 ; yes ;
; DLED:U2|oLMin[6] ; DLED:U2|Mux23 ; yes ;
; DLED:U2|oLMin[7] ; DLED:U2|Mux23 ; yes ;
; DLED:U2|oLMin[8] ; DLED:U2|Mux23 ; yes ;
; DLED:U2|oLMin[9] ; DLED:U2|Mux23 ; yes ;
; DLED:U2|oLMin[10] ; DLED:U2|Mux23 ; yes ;
; DLED:U2|oLMin[11] ; DLED:U2|Mux23 ; yes ;
; DLED:U2|oLMin[12] ; DLED:U2|Mux23 ; yes ;
; DLED:U2|oLMin[13] ; DLED:U2|Mux23 ; yes ;
; DLED:U2|oLHou[0] ; DLED:U2|Mux41 ; yes ;
; DLED:U2|oLHou[1] ; DLED:U2|Mux41 ; yes ;
; DLED:U2|oLHou[2] ; DLED:U2|Mux41 ; yes ;
; DLED:U2|oLHou[3] ; DLED:U2|Mux41 ; yes ;
; DLED:U2|oLHou[4] ; DLED:U2|Mux41 ; yes ;
; DLED:U2|oLHou[5] ; DLED:U2|Mux41 ; yes ;
; DLED:U2|oLHou[6] ; DLED:U2|Mux41 ; yes ;
; DLED:U2|oLHou[7] ; DLED:U2|Mux41 ; yes ;
; DLED:U2|oLHou[9] ; DLED:U2|Mux41 ; yes ;
; DLED:U2|oLHou[10] ; DLED:U2|Mux41 ; yes ;
; DLED:U2|oLHou[11] ; DLED:U2|Mux41 ; yes ;
; DLED:U2|oLHou[12] ; DLED:U2|Mux41 ; yes ;
; DLED:U2|oLHou[13] ; DLED:U2|Mux41 ; yes ;
; FTIMER:U3|oHouR ; GND ; yes ;
; FTIMER:U3|\SR:Ring ; FTIMER:U3|\SR:Ring~0 ; yes ;
; Number of user-specified and inferred latches = 43 ; ; ;
+-----------------------------------------------------+----------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 43 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 17 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 43 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
Info: Processing started: Mon Dec 01 18:45:53 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off timer -c timer
Info: Found 2 design units, including 1 entities, in source file DTIMER.vhd
Info: Found design unit 1: DTIMER-run
Info: Found entity 1: DTIMER
Info: Found 2 design units, including 1 entities, in source file FTIMER.vhd
Info: Found design unit 1: FTIMER-run
Info: Found entity 1: FTIMER
Info: Found 2 design units, including 1 entities, in source file DLED.vhd
Info: Found design unit 1: DLED-run
Info: Found entity 1: DLED
Info: Found 2 design units, including 1 entities, in source file TIMER.vhd
Info: Found design unit 1: TIMER-run
Info: Found entity 1: TIMER
Info: Elaborating entity "TIMER" for the top level hierarchy
Info: Elaborating entity "DTIMER" for hierarchy "DTIMER:U1"
Info: Elaborating entity "DLED" for hierarchy "DLED:U2"
Warning (10631): VHDL Process Statement warning at DLED.vhd(17): inferring latch(es) for signal or variable "oLHou", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at DLED.vhd(47): inferring latch(es) for signal or variable "oLMin", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at DLED.vhd(113): inferring latch(es) for signal or variable "oLSec", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "oLSec[0]" at DLED.vhd(113)
Info (10041): Inferred latch for "oLSec[1]" at DLED.vhd(113)
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