compvlog.do

Full Des Simulation Code

# Rev:			2.1 24Jan05 TFB - Production

# setup language: vhdl or verilog
#quietly set LANG "vhdl"
quietly set LANG "vlog"

if { $LANG == "vlog" } {
	quietly	set LANGDIR "verilog"
} else {
	quietly	set LANGDIR "vhdl"
}

quietly set CORENAME "core3des"

# setup lists of source files
quietly set rtl_supportfiles [list]
quietly set rtl_supportfiles {}
quietly set rtlfiles [list]
quietly set rtlfiles { \
"s2p" "lxf" "r2exk" "dsched" "ksched" "desmain" "des3misc" "parcheck" \
"icnt" "core3des" \
}
quietly set tb_supportfiles [list]
quietly set tb_supportfiles { \
"core3des_pkg" \
}
quietly set vtbfiles [list]
quietly set vtbfiles { \
"tb_verif_core3des" \
}
quietly set utbfiles [list]
quietly set utbfiles { \
"user_core3des tb_user_core3des" \
}

# get various bits of information from directory name
quietly set tbdir [string tolower [pwd]]
quietly set RELEASE_TYPE "eval"
quietly set rtl_rel $CORENAME	; quietly append rtl_rel	"_rtl"
quietly set nl_rel $CORENAME	; quietly append nl_rel		"_netlist"
quietly set ev_rel $CORENAME	; quietly append ev_rel		"_eval"
if {[string match */$rtl_rel/sim/* $tbdir]}	{quietly set RELEASE_TYPE "rtl"}
if {[string match */$nl_rel/sim/* $tbdir]}	{quietly set RELEASE_TYPE "netlist"}
if {[string match */$ev_rel/sim/* $tbdir]}	{quietly set RELEASE_TYPE "eval"}
quietly set FAM "rtl"
quietly set TB_TYPE "verif"
switch -glob $tbdir {
	{*_apa}		{quietly set FAM "apa"		}
	{*_pa3e}	{quietly set FAM "pa3e"		}
	{*_ax}		{quietly set FAM "ax"		}
	{*_sxa}		{quietly set FAM "sxa"		}
	{*user}		{quietly set TB_TYPE "user"	}
}

# setup constants
quietly set USER_DIR "../../../source"
quietly set NETDIR "../../../netlists"
quietly set NETBASE $CORENAME		; quietly append NETBASE "_withoutio_"
quietly set APA_NETLIST $NETBASE	; quietly append APA_NETLIST "apa"
quietly set PA3E_NETLIST $NETBASE	; quietly append PA3E_NETLIST "pa3e"
quietly set AX_NETLIST $NETBASE		; quietly append AX_NETLIST "ax"
quietly set SXA_NETLIST $NETBASE	; quietly append SXA_NETLIST "sxa"
quietly	set RTL_DIR "../../../rtl/$LANGDIR/source"
quietly set TEST_DIR "../../../rtl/$LANGDIR/test"
quietly set TBWKDIR $CORENAME
quietly append TBWKDIR "_lib"

if { $LANG == "vlog" } {
	quietly	set WKDIR "work_vlog"
	quietly	set VSUFF "v"
} else {
	quietly	set WKDIR "work_vhdl"
	quietly	set VSUFF "vhd"
	vlib $TBWKDIR
}
vlib $WKDIR

########################################################################
# procedure to compile simulation
########################################################################
proc compsim {wdir rfile rdir} {
	global LANG VSUFF incsw rf rfl skip
	quietly	set skip 0
	quietly	set rf "$rdir/$rfile.$VSUFF"
	# libero stores in "hdl" directory
	quietly	set rfl "../hdl/$rfile.$VSUFF"
	if {[file exists $rf]} {
		quietly	set incsw "+incdir+$rdir"
	} elseif {[file exists $rfl]} {
		quietly	set incsw "+incdir+../hdl"
		quietly	set rf $rfl
	} else {
		quietly	set skip 1
	}
	if {$skip == 0} {
		echo "-- Compiling file: $rf ..."
		if { $LANG == "vlog" } {
			echo "vlog -work $wdir $incsw $rf"
			vlog -work $wdir $incsw $rf
		} else {
			echo "vcom -work $wdir $rf"
			vcom -work $wdir $rf
		}
	}
}

# type of design to compile: RTL or family-specific technology
if { $FAM == "rtl" } {
	if { $LANG == "vhdl" } {
		# compile VHDL support package(s) for RTL code
		foreach f $rtl_supportfiles {compsim $WKDIR $f $RTL_DIR}
	}
	foreach f $rtlfiles {compsim $WKDIR $f $RTL_DIR}
} else {
	echo "#############################################################"
	echo "NOTE: to compile Actel netlists, the compiled Modelsim"
	echo "libraries must be setup per the Verilog and VHDL simulation"
	echo "documentation included with the Libero or Designer software"
	echo "#############################################################"
	if		{$FAM == "apa"	}	{quietly set NETLIST $APA_NETLIST	}
	elseif	{$FAM == "pa3e"	}	{quietly set NETLIST $PA3E_NETLIST	}
	elseif	{$FAM == "ax"	}	{quietly set NETLIST $AX_NETLIST	}
	elseif	{$FAM == "sxa"	}	{quietly set NETLIST $SXA_NETLIST	}
	else	{echo "-- Error! unsupported family: $FAM" ; exit		}
	compsim $WKDIR $NETLIST $NETDIR
}

# compile support utility packages for VHDL testbenches
if { $LANG == "vhdl" } {
	vmap $TBWKDIR $TBWKDIR
	foreach f $tb_supportfiles {compsim $TBWKDIR $f $TEST_DIR}
}

# compile testbench files (Verification or User)
if { $TB_TYPE == "user" } {
	foreach f $utbfiles {compsim $WKDIR $f $USER_DIR}
} else {
	foreach f $vtbfiles {compsim $WKDIR $f $TEST_DIR}
}

echo "Done with simulation compile. Have a great day!"