_primary.vhd

来自「Full Des Simulation Code」· VHDL 代码 · 共 9 行

library verilog;
use verilog.vl_types.all;
entity tb_vlog is
    generic(
        SYS_CLK_CYCLE   : integer := 50;
        USER_TB_ENABLED : integer := 1
    );
end tb_vlog;