_primary.vhd

来自「Full Des Simulation Code」· VHDL 代码 · 共 19 行

library verilog;
use verilog.vl_types.all;
entity CORE3DES is
    port(
        NRESET          : in     vl_logic;
        CLK             : in     vl_logic;
        EN              : in     vl_logic;
        CLR             : in     vl_logic;
        ED              : in     vl_logic;
        PCHK            : in     vl_logic;
        K               : in     vl_logic_vector(1 to 64);
        D               : in     vl_logic_vector(1 to 64);
        Q               : out    vl_logic_vector(1 to 64);
        QVAL            : out    vl_logic;
        KSEL            : out    vl_logic_vector(1 downto 0);
        PERR            : out    vl_logic
    );
end CORE3DES;