_primary.vhd

来自「Full Des Simulation Code」· VHDL 代码 · 共 25 行

library verilog;
use verilog.vl_types.all;
entity USER_CORE3DES is
    port(
        NRESET          : in     vl_logic;
        CLK             : in     vl_logic;
        BPASS           : in     vl_logic;
        EN              : in     vl_logic;
        CLR             : in     vl_logic;
        ED              : in     vl_logic;
        PCHK            : in     vl_logic;
        WR              : in     vl_logic;
        DIN             : in     vl_logic_vector(15 downto 0);
        CTRL            : in     vl_logic_vector(3 downto 0);
        DSEL            : in     vl_logic_vector(1 downto 0);
        DOUT            : out    vl_logic_vector(15 downto 0);
        QVAL            : out    vl_logic;
        K               : in     vl_logic_vector(1 to 64);
        D               : in     vl_logic_vector(1 to 64);
        Q               : out    vl_logic_vector(1 to 64);
        KSEL            : out    vl_logic_vector(1 downto 0);
        PERR            : out    vl_logic
    );
end USER_CORE3DES;