pattern.v

Log Shifter Gate Level Design using Verilog(IC design Lab) and Lab Note

//############################################################################
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//   (C) Copyright Laboratory System Integration and Silicon Implementation
//   All Right Reserved
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
//   2004 ICLAB(I) Course
//   Lab01      : Structural Arithmetic Design
//   Exercise_1 : 16-bits barrel shifter gate-level design
//   Author     : Wan-Chun Liao ([e-mail])
//
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
//   File Name   : PATTERN.v
//   Module Name : PATTERN
//   Release version : V1.0 (Release Date: 7-20-2004)
//
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//############################################################################

module PATTERN
(
  // OUTPUT PORT
  IN, 
  SHIFT, 
  RIGHT, 
  SIGN, 
  // INPUT PORT
  OUT
);

//---------------------------------------------------------------------
// INPUT AND OUTPUT DECLARATION
//---------------------------------------------------------------------

output 	[15:0]	IN;
output		RIGHT, SIGN;
output	[3:0]	SHIFT;
input  	[15:0]	OUT;

//---------------------------------------------------------------------
// WIRE AND REG DECLARATION
//---------------------------------------------------------------------

reg	[15:0]	IN;
reg	[3:0]	SHIFT;
reg		RIGHT, SIGN;
reg		CLK;
wire	[15:0]	C_OUT,TEMP1_C_OUT,TEMP2_C_OUT,TEMP3_C_OUT,TEMP4_C_OUT;


integer		Seed,i,j,k;
real		CYCLE;

//---------------------------------------------------------------------
// PARAMETER DECLARATION
//---------------------------------------------------------------------

parameter	Seednum = 10;

//---------------------------------------------------------------------
// PATTERN GENERATION
//---------------------------------------------------------------------

always	#(CYCLE/2.0) CLK= ~CLK;

assign	TEMP1_C_OUT = (SHIFT[3])?{{8{IN[15]}},IN[15:8]} : IN;
assign	TEMP2_C_OUT = (SHIFT[2])?{{4{TEMP1_C_OUT[15]}},TEMP1_C_OUT[15:4]} : TEMP1_C_OUT;
assign	TEMP3_C_OUT = (SHIFT[1])?{{2{TEMP2_C_OUT[15]}},TEMP2_C_OUT[15:2]} : TEMP2_C_OUT;
assign	TEMP4_C_OUT = (SHIFT[0])?{{TEMP3_C_OUT[15]},TEMP3_C_OUT[15:1]} : TEMP3_C_OUT;

assign 	C_OUT = (~RIGHT)?IN<<SHIFT:(SIGN)?TEMP4_C_OUT:IN>>SHIFT;

initial
begin
	$fsdbDumpfile("SHIFTER.fsdb");
	$fsdbDumpvars(0, TESTBED);
	CYCLE = 20;
	CLK = 0;
	Seed = Seednum;
	$display ();
	for(j=7;j>=3;j=j-1)
	begin
	CYCLE=j;
	
//////critical path/////////////////////////////
	
	RIGHT = 1'b1;
	SIGN = 1'b1;
	SHIFT = 4'b1000;
	begin
	@(posedge CLK)
		IN = 16'b1000_1000_1000_1000;	
	@(posedge CLK);
	if (OUT !== C_OUT )
	begin
	  	$display ("IN=%d, SHIFT=%d, RIGHT=%d, SIGN=%d\n",IN,SHIFT,RIGHT,SIGN);
	  	$display ("         OUT=%d\n",OUT);
	  	$display ("CORRECT: OUT=%d\n",C_OUT);
	  	$display ("Testing FAIL !!!");
	  	$finish;
	end
	end
	
////////////////////////////////////////////////	

	RIGHT = 1'b0;
	SIGN = 1'b0;
	
	for(i=0;i<=15;i=i+1)
	begin
	@(posedge CLK)
		SHIFT = i;
		IN = $random(Seed);	
	@(posedge CLK);
	if (OUT !== C_OUT )
	begin
	  	$display ("IN=%d, SHIFT=%d, RIGHT=%d, SIGN=%d\n",IN,SHIFT,RIGHT,SIGN);
	  	$display ("         OUT=%d\n",OUT);
	  	$display ("CORRECT: OUT=%d\n",C_OUT);
	  	$display ("Testing FAIL !!!");
	  	$finish;
	end
	end
	
////////////////////////////////////////////////	

	RIGHT = 1'b0;
	SIGN = 1'b1;
	for(i=0;i<=15;i=i+1)
	begin
	@(posedge CLK)
		SHIFT = i;
		IN = $random(Seed);	
	@(posedge CLK);
	if (OUT !== C_OUT )
	begin
	  	$display ("IN=%d, SHIFT=%d, RIGHT=%d, SIGN=%d\n",IN,SHIFT,RIGHT,SIGN);
	  	$display ("         OUT=%d\n",OUT);
	  	$display ("CORRECT: OUT=%d\n",C_OUT);
	  	$display ("Testing FAIL !!!");
	  	$finish;
	end
	end	

////////////////////////////////////////////////	

	RIGHT = 1'b1;
	SIGN = 1'b0;
	
	for(i=0;i<=15;i=i+1)
	begin
	@(posedge CLK)
		SHIFT = i;
		IN = $random(Seed);	
	@(posedge CLK);
	if (OUT !== C_OUT )
	begin
	  	$display ("IN=%d, SHIFT=%d, RIGHT=%d, SIGN=%d\n",IN,SHIFT,RIGHT,SIGN);
	  	$display ("         OUT=%d\n",OUT);
	  	$display ("CORRECT: OUT=%d\n",C_OUT);
	  	$display ("Testing FAIL !!!");
	  	$finish;
	end
	end

////////////////////////////////////////////////	

	RIGHT = 1'b1;
	SIGN = 1'b1;
	for(i=0;i<=15;i=i+1)
	begin
	@(posedge CLK)
		SHIFT = i;
		IN = $random(Seed);	
	@(posedge CLK);
	if (OUT !== C_OUT )
	begin
	  	$display ("IN=%d, SHIFT=%d, RIGHT=%d, SIGN=%d\n",IN,SHIFT,RIGHT,SIGN);
	  	$display ("         OUT=%d\n",OUT);
	  	$display ("CORRECT: OUT=%d\n",C_OUT);
	  	$display ("Testing FAIL !!!");
	  	$finish;
	end
	end	

/////////////////////////////////////////////////////
	
  	$display ();
  	$display ("Testing Successful at CYCLE=%f",CYCLE);
	$display ();
	end
	$finish;
end
endmodule