_primary.vhd

来自「Log Shifter Gate Level Design using Veri」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity fulladd is
    port(
        sum             : out    vl_logic;
        c_out           : out    vl_logic;
        a               : in     vl_logic;
        b               : in     vl_logic;
        c_in            : in     vl_logic
    );
end fulladd;