_primary.vhd

来自「Log Shifter Gate Level Design using Veri」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity trans is
    port(
        out0            : out    vl_logic_vector(10 downto 0);
        out1            : out    vl_logic_vector(10 downto 0);
        out2            : out    vl_logic_vector(10 downto 0);
        out3            : out    vl_logic_vector(10 downto 0);
        a               : in     vl_logic_vector(7 downto 0);
        b               : in     vl_logic_vector(7 downto 0);
        c               : in     vl_logic_vector(7 downto 0);
        d               : in     vl_logic_vector(7 downto 0);
        mode            : in     vl_logic_vector(1 downto 0)
    );
end trans;