testbed.v

Log Shifter Gate Level Design using Verilog(IC design Lab) and Lab Note

//############################################################################
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//   (C) Copyright Laboratory System Integration and Silicon Implementation
//   All Right Reserved
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
//   2004 ICLAB(I) Course
//   Lab01      : Structural Arithmetic Design
//   Exercise_1 : 16-bits barrel shifter gate-level design
//   Author     : Wan-Chun Liao ([e-mail])
//
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
//   File Name   : TESTBED.v
//   Module Name : TESTBED
//   Release version : V1.0 (Release Date: 7-20-2004)
//
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//############################################################################

`timescale 1ns/10ps

`include "PATTERN.v"
`include "SHIFTER.v"

module TESTBED;

//---------------------------------------------------------------------
// WIRE AND REG DECLARATION
//---------------------------------------------------------------------

wire 	[15:0]	IN; 
wire	[15:0]	OUT;
wire	[3:0]	SHIFT;
wire		RIGHT,SIGN;

//---------------------------------------------------------------------
// CALL MODULE
//---------------------------------------------------------------------

PATTERN SHIFT_PATTERN ( .OUT(OUT), .IN(IN), .SHIFT(SHIFT), .RIGHT(RIGHT), .SIGN(SIGN));
SHIFTER SHIFTER_GATE ( .OUT(OUT), .IN(IN), .SHIFT(SHIFT), .RIGHT(RIGHT), .SIGN(SIGN));

endmodule