mux16_stage1.v

Log Shifter Gate Level Design using Verilog(IC design Lab) and Lab Note

//############################################################################
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//   (C) Copyright Laboratory System Integration and Silicon Implementation
//   All Right Reserved
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
//   2004 ICLAB(I) Course
//   Lab01      : Structural Arithmetic Design
//   Exercise_1 : 16-bits barrel shifter gate-level design
//   Author     : Chih-Lung Chen ([e-mail])
//
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
//   File Name   : MUX16_STAGE1.v
//   Module Name : MUX16_STAGE1
//   Release version : V1.0 (Release Date: 7-20-2004)
//
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// PURPOSE: 3 to 1 mux for first stage of shifter in gate level
//          description. Sign extension is done inplicitly in order
//          to decrease delay time.
//############################################################################


module MUX16_STAGE1
(
  // Output Port
  MUX_OUT,

  // Input Port
  IN, IN_R, IN_L, RIGHT, CTRL, SIGN
);

//---------------------------------------------------------------------
// INPUT AND OUTPUT DECLARATION
//---------------------------------------------------------------------

output [15:0] MUX_OUT;
input  [15:0] IN;    // data without shift
input  [15:0] IN_R;  // right-shifted data
input  [15:0] IN_L;  // left-shifted data
input         RIGHT; // control direction of shift operation
input         CTRL;  // control if do shift or not
input         SIGN;  // sign or unsign

//---------------------------------------------------------------------
// WIRE AND REG DECLARATION
//---------------------------------------------------------------------

wire        RIGHT_INV, CTRL_INV;
wire [15:0] T1, T2, T3;

//---------------------------------------------------------------------
// GATE LEVEL DESCRIPTION OF COMBINATIONAL LOGIC
//---------------------------------------------------------------------

not  #( 0.2:0.3:0.5 , 0.2:0.3:0.5 ) ( RIGHT_INV, RIGHT );
not  #( 0.2:0.3:0.5 , 0.2:0.3:0.5 ) ( CTRL_INV, CTRL );

nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T1[0], IN_R[0], CTRL, RIGHT );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T2[0], IN_L[0], CTRL, RIGHT_INV );
nand #( 0.3:0.5:0.7 , 0.3:0.5:0.7 ) ( T3[0], IN[0], CTRL_INV );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( MUX_OUT[0], T1[0], T2[0], T3[0] );

nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T1[1], IN_R[1], CTRL, RIGHT );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T2[1], IN_L[1], CTRL, RIGHT_INV );
nand #( 0.3:0.5:0.7 , 0.3:0.5:0.7 ) ( T3[1], IN[1], CTRL_INV );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( MUX_OUT[1], T1[1], T2[1], T3[1] );

nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T1[2], IN_R[2], CTRL, RIGHT );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T2[2], IN_L[2], CTRL, RIGHT_INV );
nand #( 0.3:0.5:0.7 , 0.3:0.5:0.7 ) ( T3[2], IN[2], CTRL_INV );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( MUX_OUT[2], T1[2], T2[2], T3[2] );

nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T1[3], IN_R[3], CTRL, RIGHT );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T2[3], IN_L[3], CTRL, RIGHT_INV );
nand #( 0.3:0.5:0.7 , 0.3:0.5:0.7 ) ( T3[3], IN[3], CTRL_INV );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( MUX_OUT[3], T1[3], T2[3], T3[3] );

nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T1[4], IN_R[4], CTRL, RIGHT );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T2[4], IN_L[4], CTRL, RIGHT_INV );
nand #( 0.3:0.5:0.7 , 0.3:0.5:0.7 ) ( T3[4], IN[4], CTRL_INV );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( MUX_OUT[4], T1[4], T2[4], T3[4] );

nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T1[5], IN_R[5], CTRL, RIGHT );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T2[5], IN_L[5], CTRL, RIGHT_INV );
nand #( 0.3:0.5:0.7 , 0.3:0.5:0.7 ) ( T3[5], IN[5], CTRL_INV );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( MUX_OUT[5], T1[5], T2[5], T3[5] );

nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T1[6], IN_R[6], CTRL, RIGHT );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T2[6], IN_L[6], CTRL, RIGHT_INV );
nand #( 0.3:0.5:0.7 , 0.3:0.5:0.7 ) ( T3[6], IN[6], CTRL_INV );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( MUX_OUT[6], T1[6], T2[6], T3[6] );

nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T1[7], IN_R[7], CTRL, RIGHT );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T2[7], IN_L[7], CTRL, RIGHT_INV );
nand #( 0.3:0.5:0.7 , 0.3:0.5:0.7 ) ( T3[7], IN[7], CTRL_INV );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( MUX_OUT[7], T1[7], T2[7], T3[7] );

nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T1[8], IN_R[8], CTRL, RIGHT, SIGN );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T2[8], IN_L[8], CTRL, RIGHT_INV );
nand #( 0.3:0.5:0.7 , 0.3:0.5:0.7 ) ( T3[8], IN[8], CTRL_INV );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( MUX_OUT[8], T1[8], T2[8], T3[8] );

nand #( 0.5:0.7:0.9 , 0.5:0.7:0.9 ) ( T1[9], IN_R[9], CTRL, RIGHT, SIGN );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T2[9], IN_L[9], CTRL, RIGHT_INV );
nand #( 0.3:0.5:0.7 , 0.3:0.5:0.7 ) ( T3[9], IN[9], CTRL_INV );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( MUX_OUT[9], T1[9], T2[9], T3[9] );

nand #( 0.5:0.7:0.9 , 0.5:0.7:0.9 ) ( T1[10], IN_R[10], CTRL, RIGHT, SIGN );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T2[10], IN_L[10], CTRL, RIGHT_INV );
nand #( 0.3:0.5:0.7 , 0.3:0.5:0.7 ) ( T3[10], IN[10], CTRL_INV );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( MUX_OUT[10], T1[10], T2[10], T3[10] );

nand #( 0.5:0.7:0.9 , 0.5:0.7:0.9 ) ( T1[11], IN_R[11], CTRL, RIGHT, SIGN );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T2[11], IN_L[11], CTRL, RIGHT_INV );
nand #( 0.3:0.5:0.7 , 0.3:0.5:0.7 ) ( T3[11], IN[11], CTRL_INV );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( MUX_OUT[11], T1[11], T2[11], T3[11] );

nand #( 0.5:0.7:0.9 , 0.5:0.7:0.9 ) ( T1[12], IN_R[12], CTRL, RIGHT, SIGN );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T2[12], IN_L[12], CTRL, RIGHT_INV );
nand #( 0.3:0.5:0.7 , 0.3:0.5:0.7 ) ( T3[12], IN[12], CTRL_INV );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( MUX_OUT[12], T1[12], T2[12], T3[12] );

nand #( 0.5:0.7:0.9 , 0.5:0.7:0.9 ) ( T1[13], IN_R[13], CTRL, RIGHT, SIGN );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T2[13], IN_L[13], CTRL, RIGHT_INV );
nand #( 0.3:0.5:0.7 , 0.3:0.5:0.7 ) ( T3[13], IN[13], CTRL_INV );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( MUX_OUT[13], T1[13], T2[13], T3[13] );

nand #( 0.5:0.7:0.9 , 0.5:0.7:0.9 ) ( T1[14], IN_R[14], CTRL, RIGHT, SIGN );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T2[14], IN_L[14], CTRL, RIGHT_INV );
nand #( 0.3:0.5:0.7 , 0.3:0.5:0.7 ) ( T3[14], IN[14], CTRL_INV );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( MUX_OUT[14], T1[14], T2[14], T3[14] );

nand #( 0.5:0.7:0.9 , 0.5:0.7:0.9 ) ( T1[15], IN_R[15], CTRL, RIGHT, SIGN );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( T2[15], IN_L[15], CTRL, RIGHT_INV );
nand #( 0.3:0.5:0.7 , 0.3:0.5:0.7 ) ( T3[15], IN[15], CTRL_INV );
nand #( 0.4:0.6:0.8 , 0.4:0.6:0.8 ) ( MUX_OUT[15], T1[15], T2[15], T3[15] );

endmodule