shifter.v

来自「Log Shifter Gate Level Design using Veri」· Verilog 代码 · 共 72 行

//############################################################################
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//   (C) Copyright Laboratory System Integration and Silicon Implementation
//   All Right Reserved
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
//   2004 ICLAB(I) Course
//   Lab01      : Structural Arithmetic Design
//   Exercise_1 : 16-bits barrel shifter gate-level design
//   Author     : Chih-Lung Chen ([e-mail])
//
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
//   File Name   : SHIFTER.v
//   Module Name : SHIFTER
//   Release version : V1.0 (Release Date: 7-20-2004)
//
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//############################################################################
`include "MUX16.v"
`include "MUX16_STAGE1.v"
`include "SIGN.v"

module SHIFTER
(
  // Output Port
  OUT,

  // Input Port
  IN, SHIFT, SIGN, RIGHT
);

//---------------------------------------------------------------------
// INPUT AND OUTPUT DECLARATION
//---------------------------------------------------------------------

output [15:0] OUT;
input  [15:0] IN;
input  [3:0]  SHIFT;
input         SIGN;
input         RIGHT;

//---------------------------------------------------------------------
// WIRE DECLARATION
//---------------------------------------------------------------------

wire        EXTEND;
wire [15:0] MUX_OUT1, MUX_OUT2, MUX_OUT3;
wire [15:0] SHR8, SHR4, SHR2, SHR1;
wire [15:0] SHL8, SHL4, SHL2, SHL1;

//---------------------------------------------------------------------
// COMBINATIONAL LOGIC
//---------------------------------------------------------------------

assign SHL8 = { IN[7:0], 8'b0 };
assign SHR8 = { IN[15], IN[15], IN[15], IN[15],
                IN[15], IN[15], IN[15], IN[15], IN[15:8] };

assign SHL4 = { MUX_OUT1[11:0], 4'b0 };
assign SHR4 = { EXTEND, EXTEND, EXTEND, EXTEND, MUX_OUT1[15:4] };

assign SHL2 = { MUX_OUT2[13:0], 2'b0 };
assign SHR2 = { EXTEND, EXTEND, MUX_OUT2[15:2] };

assign SHL1 = { MUX_OUT3[14:0], 1'b0 };
assign SHR1 = { EXTEND, MUX_OUT3[15:1] };

SIGN I_SIGN(
            .EXTEND(EXTEND),
            .SIGN(SIGN),
            .IN_MSB(IN[15])   //рIN[15]