_primary.vhd

Log Shifter Gate Level Design using Verilog(IC design Lab) and Lab Note

library verilog;
use verilog.vl_types.all;
entity shifter is
    port(
        \OUT\           : out    vl_logic_vector(15 downto 0);
        \IN\            : in     vl_logic_vector(15 downto 0);
        shift           : in     vl_logic_vector(3 downto 0);
        sign            : in     vl_logic;
        right           : in     vl_logic
    );
end shifter;