median.map.rpt
来自「用verilog编辑的中值滤波器！语言旁表有注释方便理解！」· RPT 代码 · 共 740 行 · 第 1/5 页
RPT
740 行
; Source assignments for ram:r2|altsyncram:mem_rtl_1|altsyncram_hd61:auto_generated ;
+---------------------------------+--------------------+------+---------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+---------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+---------------------+
+-----------------------------------------------------------------------------------+
; Source assignments for ram:r3|altsyncram:mem_rtl_2|altsyncram_hd61:auto_generated ;
+---------------------------------+--------------------+------+---------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+---------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+---------------------+
+------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |median ;
+----------------+-------+-----------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-----------------------------------------------+
; s0 ; 0000 ; Unsigned Binary ;
; s1 ; 0001 ; Unsigned Binary ;
; s2 ; 0010 ; Unsigned Binary ;
; s3 ; 0011 ; Unsigned Binary ;
; s4 ; 0100 ; Unsigned Binary ;
; s5 ; 0101 ; Unsigned Binary ;
; s6 ; 0110 ; Unsigned Binary ;
; s7 ; 0111 ; Unsigned Binary ;
; s8 ; 1000 ; Unsigned Binary ;
; s9 ; 1001 ; Unsigned Binary ;
; s10 ; 1010 ; Unsigned Binary ;
; s11 ; 1011 ; Unsigned Binary ;
; s12 ; 1100 ; Unsigned Binary ;
; s13 ; 1101 ; Unsigned Binary ;
; s14 ; 1110 ; Unsigned Binary ;
; s15 ; 1111 ; Unsigned Binary ;
+----------------+-------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: ram:r1|altsyncram:mem_rtl_0 ;
+------------------------------------+----------------------+------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------------+------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; SINGLE_PORT ; Untyped ;
; WIDTH_A ; 8 ; Untyped ;
; WIDTHAD_A ; 11 ; Untyped ;
; NUMWORDS_A ; 1728 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; UNUSED ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; CBXI_PARAMETER ; altsyncram_hd61 ; Untyped ;
+------------------------------------+----------------------+------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: ram:r2|altsyncram:mem_rtl_1 ;
+------------------------------------+----------------------+------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------------+------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; SINGLE_PORT ; Untyped ;
; WIDTH_A ; 8 ; Untyped ;
; WIDTHAD_A ; 11 ; Untyped ;
; NUMWORDS_A ; 1728 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; UNUSED ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
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